Multi-Bank Memory Status Feedback via Segmented Registers
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Solution Overview
Problem
Current two-terminal memory technologies, such as resistive memory, face challenges in providing real-world benefits for electronic devices due to limitations in status feedback and control mechanisms, leading to inefficiencies in memory operations and resource utilization.
Innovation Solution
The implementation of a multi-bank memory device with status registers that provide bank-specific status feedback, allowing for independent control and monitoring of memory banks, enabling more efficient operation and resource management through mechanisms like LPDDR3 communication protocols and mode registers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a single status register is used for all memory banks, then device complexity is reduced, but productivity decreases due to inability to perform concurrent operations on different banks
Solution Approach 1:
The status register is segmented into multiple independent status registers, with each register dedicated to monitoring a specific memory bank. This segmentation allows the memory controller to query and monitor the status of individual banks independently, enabling concurrent operations on different banks without waiting for a single shared status register to update, thereby improving memory operation throughput.
2Ease of operation
If bank-specific status feedback is implemented, then ease of operation improves for individual bank control, but device complexity increases due to additional status registers and addressing mechanisms
Solution Approach 1:
An address register is introduced as an intermediary component that stores the address of the target memory bank. When a read operation is requested, the controller first loads the bank address into the address register, which then serves as a mediator to route the status query to the correct bank-specific status register. This intermediary mechanism simplifies the control process by providing a clear two-step procedure (load address, then read status) while managing the complexity of multiple status registers.
3Productivity
If multiple status registers are used for different memory bank subsets, then productivity increases through concurrent operations, but loss of information increases due to more status registers that need to be managed
Solution Approach 1:
Each memory bank has its dedicated status register providing real-time feedback on the completion status of operations. This feedback mechanism allows the memory controller to continuously monitor multiple banks simultaneously and initiate new operations on banks that have completed their current operations, thereby enabling concurrent operations and improving productivity while maintaining clear visibility of all operation statuses.
Data Source
AI summary
Providing for a multi-bank memory with bank-specific status feedback is described herein. By way of example, the multi-bank memory can be configured to output an availability status, pass/fail status, error correction status, or the like, for subsets of multiple memory banks. In some embodiments, the non-volatile memory can provide global status information, representing a status of all banks commonly in conjunction with bank-specific status information. Further, the subject disclosure provides addressing techniques for identifying particular banks of memory, and obtaining status information for subsets of the memory banks, or performing memory operations on targeted subsets of the memory banks.