Multi-Bank Memory with Expanded Address Bus and Status Registers
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current memory technologies face limitations in achieving high-density, non-volatile memory with efficient communication interfaces and granular status feedback, leading to suboptimal performance and resource utilization in multi-bank memory systems.
Innovation Solution
The implementation of a multi-bank memory system with resistive-switching memory technology, featuring a high-speed communication interface with a modified LPDDR bus and status registers for real-time feedback, allowing for concurrent operations and efficient error correction across subsets of memory banks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional memory technologies are used, then existing memory structures can be maintained, but high-density non-volatile memory with efficient communication interfaces cannot be achieved
Solution Approach 1:
The memory system is divided into multiple independently addressable banks (16 or more), each capable of concurrent operations. This segmentation allows parallel access to different memory regions, improving communication efficiency while maintaining high density through the expanded 30-bit address space that can uniquely identify locations across all banks.
Solution Approach 2:
The patent extends the address bus from conventional widths to 30 bits, adding addressing dimensions that enable direct access to vastly expanded memory spaces. This dimensional expansion in address space allows the system to accommodate high-density non-volatile memory while maintaining efficient communication through direct addressing without requiring additional interface complexity.
2Productivity
If multi-bank memory systems are implemented, then throughput can be increased, but resource utilization becomes suboptimal without granular status feedback
Solution Approach 1:
Status registers are implemented for each memory bank to provide real-time feedback on operational state, busy conditions, and error status. This granular feedback mechanism enables the host system to make informed decisions about resource allocation and timing, optimizing utilization of the multi-bank structure while maintaining high throughput through concurrent operations.
Solution Approach 2:
The status registers provide advance information about bank availability and operational state before memory operations are initiated. This preliminary status information allows the host to pre-coordinate access patterns and minimize wait states, improving overall resource utilization while maintaining the high throughput enabled by multiple concurrent banks.
3Speed
If conventional bus interfaces are used, then existing communication protocols can be maintained, but high-speed communication with expanded addressing capability cannot be achieved
Solution Approach 1:
The modified LPDDR bus interface is designed to handle multiple functions including high-speed data transfer, 30-bit address transmission, and status register access through a unified protocol. This multi-functional design achieves high-speed communication and expanded addressing capability without proportionally increasing interface complexity, as the same physical bus infrastructure supports multiple operational modes and address spaces.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables high read and write performance, increased throughput, and efficient resource utilization by providing granular status information, enabling the host to manage memory operations more effectively and target error correction routines accurately.
Implementation Method 1
resistive-switching memory technology... Two-terminal memory devices can be controlled by applying a stimulus at one or both of the pair of conductive contacts
Data Source
AI summary
Providing for an electronic memory apparatus having high-density, non-volatile memory arrays in conjunction with a high-speed communication interface is disclosed herein. In some embodiments, the electronic memory apparatus can include multiple banks of two-terminal memory, communicatively connected to a modified dynamic random access memory bus and configured to operate according to a modified communication protocol. In one or more embodiments, the high-speed communication interface can comprise more than ten command and address pins to identify individual memory banks (or subsets of memory banks) of the multiple banks of memory, to facilitate bank-specific addressing for memory array operations. In some embodiments, the electronic memory can facilitate status information for subsets of memory banks to facilitate informed array operations, increasing duty cycle of the memory device.