Multi-bank Non-volatile Memory with Interleaved High-speed Bus
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Solution Overview
Problem
Current electronic memory technologies face limitations in achieving high-speed data throughput and flexibility in configuration, particularly in two-terminal memory systems, which restrict their integration with existing electronic systems and efficiency in error correction and resource utilization.
Innovation Solution
A multi-bank memory apparatus with a high-speed interface, utilizing resistive-switching memory and a standard LPDDR bus, capable of generating bank-specific and global status information, and allowing for inter-bank configurability, enabling efficient interleaved operations and advanced error correction techniques.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If a standard LPDDR bus is used for integration with existing electronic systems, then ease of operation and plug-and-play integration are improved, but device complexity increases due to the need for expanded command and address bus to address 128 or more memory banks
Solution Approach 1:
The memory system is divided into 128 or more independent memory banks, each addressable through the expanded command and address bus. This segmentation allows the standard LPDDR bus to maintain compatibility with existing systems while the expanded addressing capability enables access to the large number of banks, resolving the contradiction between ease of integration and device complexity.
2Productivity
If 128 or more distinct banks of resistive-switching memory are implemented, then productivity and data throughput are improved, but device complexity increases due to the need for interleave-processing circuitry
Solution Approach 1:
The memory controller performs preliminary actions by pre-fetching and buffering data from multiple memory banks before it is actually needed. This allows the system to maintain high data throughput across 128 or more banks without requiring complex real-time interleave-processing circuitry, as the data preparation work is done in advance.
3Reliability
If bank-specific status information is generated for each memory bank, then reliability and error correction capabilities are improved, but device complexity and loss of information increase due to the extensive status feedback required
Solution Approach 1:
Status information from multiple memory banks is merged and aggregated into consolidated status registers. Instead of requiring separate status feedback circuitry for each of the 128 or more memory banks, the system combines status information at regular intervals, maintaining comprehensive error correction capabilities while significantly reducing the complexity of status feedback circuitry.
4Use of energy by moving object
If resistive-switching memory is used instead of conventional CMOS NAND or NOR memory, then use of energy and power consumption are reduced, but manufacturing precision requirements increase for the two-terminal device structure
Solution Approach 1:
The patent employs parameter changes in the resistive-switching memory cells, utilizing materials and structures that achieve the desired low-power operation with relaxed manufacturing tolerances. By adjusting key parameters such as material composition, device geometry, and operating conditions, the system achieves reduced power consumption without requiring extremely tight manufacturing precision for the two-terminal structure.
Data Source
AI summary
Providing for a memory apparatus comprising multiple banks of non-volatile memory and a high-speed data bus is described herein. By way of example, the memory apparatus can employ a standard or near-standard DRAM bus as an interface to high-performance two-terminal memory arrays. Interleaved operation can facilitate throughputs over 2gigabytes/second, in various embodiments, and larger throughputs in at least some embodiments, by interleaving multiple memory banks that are separately addressed via one or more mode registers, referred to as an index register(s). Further, the memory apparatus can have one or two terabytes of total storage, with capacity to increase storage volume. According to various embodiments, the memory apparatus can operate with a standard DRAM controller, or a memory controller configured with a DRAM communication protocol, modified in software or firmware to match configurations of the non-volatile memory employed for the multiple banks of memory.