Multi-Bank Queuing Architecture for High Bandwidth On-Chip Memory

The memory buffer is divided into multiple independent banks (e.g., Bank 0, Bank 1, Bank 2, Bank 3), each capable of handling read or write operations independently. This segmentation allows simultaneous access to multiple banks, thereby increasing overall bandwidth without requiring each individual bank to handle the full port bandwidth, reducing the complexity burden on any single memory component.

The patent transitions from a single-dimensional sequential access model to a multi-dimensional parallel access model by organizing memory into multiple banks that can be accessed simultaneously. This dimensional change in memory architecture enables the system to achieve higher bandwidth by exploiting parallelism across banks rather than increasing clock frequency or data bus width within a single bank.

By segmenting the memory into multiple banks, the system achieves higher effective bandwidth through parallel operations at a moderate clock frequency, rather than requiring a single bank to operate at a higher clock frequency. This approach reduces manufacturing cost by avoiding the need for high-speed memory components while maintaining the required data throughput.

The patent employs periodic alternating access patterns across multiple banks (e.g., even banks for writes, odd banks for reads in alternating cycles), which distributes the bandwidth requirement over time and across multiple memory units. This periodic action allows the system to achieve high average bandwidth without requiring any single memory bank to operate at peak speeds continuously, thereby reducing manufacturing cost.

The memory system is segmented into multiple banks that can be accessed in parallel with standard-width data buses. This segmentation effectively multiplies the bandwidth capacity without requiring each individual data bus to be wider, thereby maintaining simpler bus design and reducing device complexity while achieving the required bandwidth.

The patent merges multiple narrower data bus channels (one for each memory bank) into a unified high-bandwidth system. By combining the throughput capacity of multiple banks accessed in parallel, the system achieves equivalent or superior bandwidth to a single wide data bus, but with reduced complexity since each individual bus remains narrow and manageable.

The memory is segmented into multiple banks that can independently handle read and write operations simultaneously. This segmentation isolates potential access conflicts to individual banks rather than creating system-wide conflicts, allowing high productivity through parallel operations while maintaining reliability by preventing conflicts at the bank level through proper address routing.

The patent implements dynamic bank selection and access arbitration mechanisms that adaptively route read and write operations to appropriate banks based on current system state. This dynamic control enables simultaneous read and write operations across different banks, maximizing productivity while preventing access conflicts through intelligent resource management and conflict avoidance strategies.