Multi-bank Distributed Shared Memory for Artificial Reality
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Solution Overview
Problem
Artificial reality systems face challenges in achieving concurrent and low-latency memory access while minimizing power consumption, particularly in applications like virtual and augmented reality where extensive memory usage is required, often leading to high latency and power consumption costs.
Innovation Solution
The implementation of a multi-bank, multi-port distributed shared memory system on a System on a Chip (SoC) that allows for concurrent access to multiple memory banks with varying latency and power consumption attributes, reducing the need for locking or arbitration by strategically associating memory banks with specific components and using networks to connect them, thereby optimizing performance and power efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If extensive memory usage is implemented in artificial reality systems, then memory capacity is improved, but memory latency increases
Solution Approach 1:
The memory system is divided into multiple independent memory banks (first memory bank, second memory bank, etc.) that can be accessed concurrently. Each memory bank operates independently with its own access port, allowing the system to provide extensive total memory capacity while maintaining low latency through parallel access operations across different banks.
2Speed
If concurrent memory access is enabled, then access speed is improved, but power consumption increases
Solution Approach 1:
The system implements differentiated access characteristics for different memory banks, where each bank can be accessed with varying latency and power consumption attributes. This allows the system to optimize power usage by directing access patterns to appropriate banks based on their characteristics, enabling concurrent access while managing overall power consumption efficiently.
3Productivity
If memory banks are strategically associated with specific components, then access efficiency is improved, but system complexity increases
Solution Approach 1:
Memory banks are pre-associated with specific components or subsystems during system design and configuration. This preliminary association establishes optimized access paths and reduces the need for dynamic arbitration or locking mechanisms during operation, thereby improving access efficiency while keeping the control logic relatively simple.
Data Source
AI summary
This disclosure describes various examples of a system which uses a multi-bank, multi-port shared memory system that may be implemented as part of a system on a chip. The shared memory system may have particular applicability in the context of an artificial reality system, and may be designed to have distributed or varied latency for one or more memory banks and/or one or more components or subsystems within the system on a chip. The described shared memory system may be logically a single entity, but physically may have multiple memory banks, each accessible by any of a number of components or subsystems. In some examples, the memory system may enable concurrent, common, and/or shared access to memory without requiring, in some situations, full locking or arbitration.