Multi-Bank SRAM Bit Line Pre-Charge Sequencing for Peak Current Control
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Solution Overview
Problem
Existing semiconductor memory systems face challenges in managing power consumption during wake-up operations, particularly in low power modes, leading to high peak current draw that can cause component failures and inefficiencies.
Innovation Solution
Implementing a delay element in the bit line pre-charge circuit to sequence the precharging of bit lines in a memory bank, reducing peak current by ensuring bit lines are powered up sequentially rather than simultaneously.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If bit lines are precharged simultaneously during wake-up operations, then memory cells are prepared for operation quickly, but peak current draw increases causing component failures
Solution Approach 1:
The patent divides the simultaneous precharge operation into segmented sequential operations across multiple banks. Each bank's bit lines are precharged in sequence rather than all at once, breaking the peak current event into manageable segments that occur at different times controlled by delay elements
2Power
If delay elements are added to sequence bit line precharging, then peak current draw is reduced, but circuit complexity increases
Solution Approach 1:
The patent introduces dynamic control elements (delay elements) that adjust the timing of precharge signals dynamically. These elements allow the circuit to adapt its operation mode between simultaneous precharge and sequential precharge based on power management requirements, adding controlled complexity only when needed
3Power
If sequential precharging is implemented across memory banks, then power management is optimized, but operation time increases
Solution Approach 1:
The patent applies different precharge strategies to different banks based on their specific requirements. Some banks may use simultaneous precharge while others use sequential precharge, allowing optimization at the local bank level rather than forcing a uniform approach across the entire memory array
Data Source
AI summary
Systems and methods are provided for controlling a wake-up operation of a memory circuit. The memory circuit is configured to precharge the bit lines of a memory array sequentially during wakeup. A sleep signal is received by the first bit line of a memory cell and then a designed delay occurs prior to the precharge of a second complementary bit line. The sleep signal may then precharge the bit lines of a second memory cell with further delay between the precharge of each bit line. The memory circuit is configured to precharge both bit lines of a memory cell at the same time when an operation associated with that cell is designated.