Multi-Baud Clock Generator Using Digital Oversampling Division

Solution Overview

Problem

Current clock generators for Gigabit Ethernet and Fast Ethernet physical layers require multiple phase-lock loop circuits and analog mixers, leading to high power consumption and large chip area, hindering miniaturization and cost reduction.

Innovation Solution

A clock signal generator using a source clock signal generator that outputs multiple source clock signals with the same frequency, processed by digital logic circuits through oversampling technology to achieve synchronous clock signals for various baud rates, reducing the need for multiple phase-lock loop circuits and analog mixers.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If multiple phase-lock loop circuits and analog mixer circuits are used to support multiple baud rates, then the clock generator can cover multiple transmission rates (125 MBaud and 10 MBaud), but power consumption increases and chip area increases

Engineering Contradiction:

Improvecoverage of multiple transmission ratesVSAvoidpower consumption

Core Design Contradiction:

Adaptability or versatilityVSUse of energy by stationary object

Solution Approach 1:

A single phase-lock loop circuit is designed to perform multiple functions by generating multiple source clock signals that can be divided to support different baud rates (125 MBaud and 10 MBaud), replacing the need for separate phase-lock loop circuits for each rate

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

Analog mixer circuits are replaced with digital frequency dividing circuits, substituting analog signal processing with digital logic operations to reduce power consumption and simplify the system architecture

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

2Adaptability or versatility

If multiple phase-lock loop circuits and analog mixer circuits are used to support multiple baud rates, then the clock generator can cover multiple transmission rates (125 MBaud and 10 MBaud), but chip area increases

Engineering Contradiction:

Improvecoverage of multiple transmission ratesVSAvoidchip area

Core Design Contradiction:

Adaptability or versatilityVSArea of stationary object

Solution Approach 1:

A single phase-lock loop circuit is designed to perform multiple functions by generating multiple source clock signals that can be divided to support different baud rates (125 MBaud and 10 MBaud), replacing the need for separate phase-lock loop circuits for each rate

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

Multiple frequency dividing functions are integrated into a single digital logic circuit module, combining what would traditionally require separate analog mixer circuits into one unified digital structure, thereby reducing chip area

Inventive Principle:

Principle #5Merging (Combining)

3Adaptability or versatility

If multiple phase-lock loop circuits are used for different baud rates, then each transmission rate can have dedicated clock generation, but device complexity increases

Engineering Contradiction:

Improvesupport for different baud ratesVSAvoidnumber of phase-lock loop circuits

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

A single phase-lock loop circuit is designed to perform multiple functions by generating multiple source clock signals that can be divided to support different baud rates (125 MBaud and 10 MBaud), replacing the need for separate phase-lock loop circuits for each rate

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The clock generation function is segmented into two independent stages: a shared phase-lock loop circuit that generates source clock signals, and separate frequency dividing circuits that process these signals for different baud rates, allowing flexibility without increasing overall system complexity

Inventive Principle:

Principle #1Segmentation

Data Source

PatentUS8823437B2Clock signal generator

Publication Date: 2014.09.02 HUAWEI TECH CO LTD

AI summary

Embodiments of the present invention provide a clock signal generator, and the clock signal generator is applied to a physical layer subsystem supporting data transmission at multiple baud rates. The clock signal generator includes: a source clock signal generator, and two or more processors connected to an output end of the source clock signal generator; where the source clock signal generator outputs multiple source clock signals with the same frequency according to a reference signal of a reference clock in the subsystem; the processors perform frequency dividing processing on the multiple source clock signals through a digital logic circuit according to an oversampling technology, to obtain a synchronous clock signal corresponding to a baud rate of data transmission in the subsystem, so as to implement timing and transceiving functions when data is transmitted at the baud rate.