Multi-Bit Voltage-to-Delay ADC Circuit Without Parallel TDC Paths
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional delay domain analog-to-digital converters face issues with flicker noise, common mode rejection ratio degradation, and increased power consumption due to separate double differential pairs and parallel time-to-digital converter paths, which affect the spurious free dynamic range and chip area efficiency.
Innovation Solution
The proposed solution involves a multi-bit input buffer generating differential residues relative to zero-crossing references, with zero-crossing comparators and folding logic to encode a digital output word, eliminating the need for parallel TDC circuitry and reducing flicker noise by chopping the residues rather than the input signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate double differential pairs are used in conventional delay domain ADCs, then the common mode rejection ratio is degraded, but the circuit complexity increases and power consumption increases
Solution Approach 1:
The patent combines multiple differential pairs into a shared architecture where a single set of differential pairs serves multiple comparison functions across different input ranges. This merging eliminates the need for separate double differential pairs, reducing circuit complexity while maintaining common mode rejection ratio through the unified design.
Solution Approach 2:
The differential pairs are designed to perform multiple functions simultaneously - comparing input signals across different zones and ranges using a single shared structure. This multi-functionality reduces the overall number of components needed while maintaining the required common mode rejection performance.
2Measurement precision
If parallel time-to-digital converter paths are used, then the spurious free dynamic range is improved, but the chip area increases
Solution Approach 1:
The patent segments the conversion function across multiple serial stages rather than using parallel paths. Each stage processes a portion of the conversion function sequentially, achieving the required spurious free dynamic range through staged processing without requiring multiple simultaneous parallel converter paths, thus reducing chip area.
Solution Approach 2:
The patent transitions from a parallel architecture (multiple simultaneous paths) to a serial-time dimension approach, where conversion occurs through multiple sequential stages in time. This dimensional change from spatial parallelism to temporal serialism reduces chip area while maintaining measurement precision.
3Measurement precision
If conventional delay domain ADC architecture is used, then the conversion performance is achieved, but the power consumption increases
Solution Approach 1:
The patent merges multiple functional blocks into a shared architecture where a single set of differential pairs and associated circuitry serves multiple conversion functions. This consolidation reduces the total number of active components and their associated power consumption while maintaining conversion performance through the efficient shared design.
Data Source
AI summary
An analog-to-digital converter circuit incorporating includes a multi-bit input buffer having a differential input and configured to generate, at a plurality of differential outputs, a plurality of residues of a differential input sample relative to a corresponding plurality of zero-crossing references. Chopping stages chop the residues, for example with a pseudo-random binary sequence. The circuit further includes zero-crossing comparators, each with differential inputs coupled to receive one of the chopped residues. The zero-crossing comparators are in an ordered sequence of zone thresholds within the input range of the circuit. Folding logic circuitry has inputs coupled to outputs of the comparators, and outputs a delay domain signal indicating a magnitude of the one of the residues relative to a nearest zone threshold. Digital stage circuitry generates a digital output word representing the received input sample responsive to the comparator outputs and the delay domain signal.