Multi-Bit Operation Cells for Calibrated Resistive MAC Processing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing neural network operations, particularly in the context of multiply-accumulate (MAC) operations, face inefficiencies in processing multi-bit inputs and weights, and there are challenges in accurately calibrating weight resistances due to process variations, leading to errors in calculations.
Innovation Solution
A multi-bit operation device comprising multi-bit cells with a memory to store weight resistances, a current source to generate weight voltages, multiplexers to select between weight and fixed voltages, capacitors to generate charge data, and a switch for calibration, along with a converter to digitize the sum data, enabling accurate calibration and reduced power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If weight resistance is used for multi-bit processing, then processing efficiency is improved, but accuracy deteriorates due to process variations
Solution Approach 1:
The patent performs weight calibration before actual neural network operations to pre-compensate for process variations. The calibration module measures actual weight resistance values and stores corrected calibration values, which are then used during MAC operations to eliminate accuracy errors caused by manufacturing variations.
Solution Approach 2:
The calibration module continuously monitors and adjusts weight resistance values by comparing measured values with target values. This feedback mechanism allows the system to detect and correct deviations caused by process variations, maintaining calculation accuracy while using resistance-based multi-bit processing.
2Adaptability or versatility
If conventional digital computers are used for operations, then versatility is maintained, but processing speed deteriorates
Solution Approach 1:
The patent replaces conventional digital multiplication and addition operations with analog voltage-based MAC operations. By using current sources, resistors, and capacitors to perform multiply-accumulate operations directly in the analog domain, the system achieves faster processing speeds while maintaining the ability to perform various neural network operations.
3Measurement precision
If calibration is performed to improve accuracy, then measurement precision is improved, but power consumption increases
Solution Approach 1:
The calibration operation is performed periodically or initially before neural network operations, rather than continuously during processing. This allows the system to achieve accurate weight calibration while minimizing power consumption during actual computation, as the power-intensive calibration phase occurs only when needed.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances the accuracy of neural network operations by correcting weight resistance errors and optimizing power usage, improving the efficiency of multi-bit processing without direct multiplication operations.
Implementation Method 1
a memory configured to store a weight resistance corresponding to a multi-bit weight
Implementation Method 2
a current source configured to apply current to the memory such that a weight voltage is generated from the weight resistance
Implementation Method 3
a plurality of capacitors connected respectively to the plurality of multiplexers and each configured to store a separate weight capacitance and generate charge data by performing an operation on the output signal and the weight capacitance
Data Source
Figure 1
Figure 2
Figure 3A
AI summary
A multi-bit operation device includes a plurality of multi-bit cells, and a converter configured to convert second sum data into digital data, wherein the second sum data is generated by summing pieces of first sum data output from each of the plurality of multi-bit cells, and each of the plurality of multi-bit cells comprises a memory configured to store a weight resistance corresponding to a multi-bit weight, a current source configured to apply current to the memory such that a weight voltage is generated from the weight resistance, a plurality of multiplexers connected to one another in parallel and connected to the memory in series and each configured to output a signal of one of the weight voltage and a first fixed voltage, based on a multi-bit input, a plurality of capacitors connected respectively to the plurality of multiplexers and each configured to store a separate weight capacitance and generate charge data by performing an operation on the output signal and the weight capacitance, a bit line configured to output first sum data generated by summing pieces of charge data generated by each of the plurality of capacitors, and a switch of which an end is connected to the memory and an opposite end to the end is connected to the bit line.