Multi-bit CIM Arrays with MSB Voltage Optimization
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Solution Overview
Problem
Data transfer bottlenecks in computer hardware during neural network operations lead to inefficiencies in processing time, power consumption, and accuracy in machine learning tasks like facial recognition, as large amounts of data need to be transferred between processing circuits and memory for thousands of calculations.
Innovation Solution
Multi-bit compute-in-memory (CIM) arrays with bit cell circuits optimized for accuracy and power efficiency, where a higher supply voltage is applied to most-significant bit cells to increase voltage differences and accuracy, and smaller capacitance is used to minimize energy consumption, allowing for simultaneous operations across thousands of calculations without data transfer bottlenecks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a higher supply voltage is applied to MSB bit cell circuits to increase voltage difference and accuracy, then accuracy of ADC determining pop-count is improved, but energy consumption increases
Solution Approach 1:
The patent applies different supply voltages to different bit positions within the same CIM array. Specifically, MSB (most significant bit) bit cell circuits receive a higher supply voltage (e.g., 1.2V) while LSB (least significant bit) bit cell circuits receive a lower supply voltage (e.g., 0.9V). This local differentiation optimizes accuracy where it matters most (MSB) while reducing overall energy consumption.
Solution Approach 2:
The patent changes the supply voltage parameter selectively across different bit cell circuits based on their significance. By adjusting the voltage parameter according to bit position (MSB vs LSB), the system achieves optimal measurement precision for critical bits while minimizing energy usage across the entire array.
2Measurement precision
If voltage difference is increased in MSB bit cell circuits to improve accuracy, then accuracy of CIM array circuit output is improved, but power consumption increases
Solution Approach 1:
The patent implements local quality by providing enhanced voltage (and thus enhanced accuracy) only to MSB bit cell circuits where it is most critical for output accuracy, while using reduced voltage in LSB circuits where accuracy requirements are lower, thereby optimizing the trade-off between overall accuracy and power consumption.
Solution Approach 2:
The patent changes the voltage parameter selectively based on bit significance, applying higher voltage to MSB circuits to increase voltage difference and improve output accuracy, while applying lower voltage to LSB circuits to reduce overall power consumption of the stationary bit cell circuits.
3Device complexity
If all bit cell circuits use the same supply voltage, then device simplicity is maintained, but accuracy of MSB is insufficient for high-precision applications
Solution Approach 1:
The patent transitions from uniform voltage distribution to local quality-based voltage distribution, where MSB bit cell circuits receive higher supply voltage for enhanced accuracy while LSB circuits receive lower voltage. This resolves the contradiction by accepting increased device complexity (multiple voltage rails) only where necessary to achieve the required measurement precision.
Data Source
AI summary
A bit cell circuit of a most-significant bit (MSB) of a multi-bit product generated in an array of bit cells in a compute-in-memory (CIM) array circuit is configured to receive a higher supply voltage than a supply voltage provided to a bit cell circuit of another bit cell corresponding to another bit of the multi-bit product. A bit cell circuit receiving a higher supply voltage increases a voltage difference between increments of an accumulated voltage, which can increase accuracy of an analog-to-digital converter determining a pop-count. A bit cell circuit of the MSB in the CIM array circuit receives the higher supply voltage to increase accuracy of the MSB which increases accuracy of the CIM array circuit output. A capacitance of a capacitor in the bit cell circuit of the MSB is smaller to avoid an increase in energy consumption due to the higher voltage.