Multi-bit Memory Buffer Program Method for Reliability
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Solution Overview
Problem
As semiconductor memory devices increase in data bits per cell, reliability is compromised due to unintended threshold voltage variations from coupling between adjacent memory cells, making it difficult to securely store and read multi-bit data.
Innovation Solution
The implementation of a multi-bit memory device with a memory controller that employs an address scramble technique, a 1-step, coarse, and fine program operation sequence, along with an error correction code (ECC) circuit to manage coupling effects and ensure accurate data storage and retrieval.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the data bits per memory cell are increased to enhance storage density, then the storage capacity is improved, but the reliability deteriorates due to unintended threshold voltage variations from coupling between adjacent memory cells
Solution Approach 1:
The memory cell array is divided into a first memory region and a second memory region. The first memory region stores data in a first state (e.g., lower threshold voltage range) while the second memory region stores data in a second state (e.g., higher threshold voltage range). This spatial segmentation of storage states reduces coupling effects between adjacent memory cells, allowing multi-bit storage while maintaining reliability through distinct threshold voltage distributions.
2Reliability
If an address scramble technique and multi-step program operation are implemented to reduce coupling effects, then the data storage reliability is improved, but the device complexity increases
Solution Approach 1:
Before performing the main program operation to write data to the second memory region, the controller first performs a buffer program operation to write data to the first memory region. This preliminary action prepares the threshold voltage distribution in advance, creating a foundation that reduces coupling effects during the subsequent main programming operation, thereby improving reliability while managing complexity through staged execution.
Solution Approach 2:
The controller changes the programming parameters by implementing a multi-step program operation sequence (buffer program operation followed by main program operation) with different voltage conditions and timing. This parameter change approach allows precise control over threshold voltage distribution, reducing coupling effects and improving data storage reliability without requiring fundamentally more complex circuitry.
3Reliability
If a buffer memory is used to store data before programming, then the data integrity is improved, but the device complexity and buffer memory size increase
Solution Approach 1:
The buffer memory is divided into a first buffer region and a second buffer region. The first buffer region temporarily stores data intended for the first memory region, while the second buffer region stores data for the second memory region. This segmentation allows the controller to manage buffer contents efficiently, reducing the total buffer size requirement while maintaining data integrity through organized temporary storage before programming operations.
Solution Approach 2:
After the buffer program operation completes and data is successfully written to the first memory region, the controller can discard the data from the first buffer region and reuse that buffer space for subsequent operations. This recovering of buffer space dynamically reduces the peak buffer memory size requirement while maintaining data integrity during the programming process.
Data Source
AI summary
A data storage device includes a multi-bit memory device including a memory cell array, the memory cell array including a first memory region and a second memory region, and a memory controller including a buffer memory and configured to control the multi-bit memory device. The memory controller is configured to control the multi-bit memory device to execute a buffer program operation in which data stored in the buffer memory is stored in the first memory region, and to control the multi-bit memory device to execute a main program operation in which the data stored in the first memory region is stored in the second memory region. The memory controller is further configured to generate parity data based upon the data stored to the first region, the parity data being copied from the first memory region to the second memory region via the main program operation.