Multi-bit Nonvolatile Memory Recessed Gate Structure
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Solution Overview
Problem
Current nonvolatile memory devices face challenges in efficiently storing multi-bit data without increasing the physical size of unit cells, particularly in addressing short channel effects and optimizing storage capacity.
Innovation Solution
The design involves a semiconductor substrate with recessed regions and insulating layers, including ONO layers, where impurity regions form specific angles with gate electrodes, allowing for selective data storage by voltage application, and the use of nano-crystal or charge-trapping dielectric films to enhance storage capacity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple insulating layers are used to form a gate insulating layer for charge storage, then nonvolatile memory functionality is achieved, but device complexity increases
Solution Approach 1:
The gate insulating layer is segmented into multiple functional insulating layers: a first insulating layer (charge trapping layer, e.g., silicon nitride) for charge storage, a second insulating layer (tunnel insulating layer, e.g., silicon oxide) for charge injection/extraction, and a third insulating layer (blocking insulating layer) for preventing charge leakage. Each layer performs a specific function, enabling nonvolatile memory operation while maintaining structured complexity.
2Reliability
If a multi-bit memory device stores data on sidewalls of a trench region to address short channel effects, then device reliability improves, but manufacturing precision requirements increase
Solution Approach 1:
The invention transitions from planar charge storage to three-dimensional storage by forming charge trapping insulating layers on the sidewalls of recessed regions (trenches) in the semiconductor substrate. This vertical/dimensional approach allows multiple bit storage locations (first, second, third, and fourth charge trapping insulating layers on different sidewalls) while effectively reducing the impact of short channel effects through the trench structure.
3Quantity of substance
If impurity regions form a relative angle less than 120° with respect to the gate electrode center, then storage capacity increases, but device geometry becomes more complex
Solution Approach 1:
The impurity regions are strategically positioned at specific angular locations (less than 120° relative angle with respect to the gate electrode center) to optimize charge storage efficiency. This local optimization of impurity region placement enhances the storage capacity by concentrating charge trapping in geometrically favorable positions while maintaining overall device functionality.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables the storage of multiple bits in a single unit cell, improving storage capacity and packing density while maintaining a compact device size, and allows for independent storage and erasure of data.
Implementation Method 1
charges can be injected into the charge trapping insulating layer by Fouler-Nordheim tunneling or hot carrier injection to form a stored logical value
Implementation Method 2
charges can be injected into the charge trapping insulating layer by Fowler-Nordheim tunneling or hot carrier injection to form a stored logical value
Implementation Method 3
The stored charge is erased by discharging electrons from the charge trapping insulating layer or by injecting holes into the charge trapping insulating layer
Data Source
AI summary
Multi-bit nonvolatile memory devices and related methods of manufacturing the same are described. In some multi-bit nonvolatile memory devices, a semiconductor substrate has a recessed region defined therein. An insulating layer, which can include an ONO layer, is configured to store data within programming regions therein, and covers a sidewall and a lower surface of the recess region. A gate electrode is on the insulating layer in the recessed region. At least one pair of impurity regions are in the semiconductor substrate. The impurity regions adjoin a side surface of the insulating layer in the recess region and form a relative angle that is less than 120° therebetween with respect to a center of the gate electrode.