Multi-bit Non-volatile Memory with Trench-defined Fins
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Solution Overview
Problem
Current non-volatile memory devices face limitations in increasing capacity and operation speed due to micro-pattern processing technologies, with existing solutions either being limited to 2-bit mode or unable to effectively suppress the short channel effect, restricting device integration and performance.
Innovation Solution
A non-volatile memory device design featuring fins defined by trenches in a semiconductor substrate, with gate electrodes as spacers and storage nodes capable of storing electric charge, allowing for multi-bit and multi-level operations while suppressing the short channel effect through careful placement and insulation of storage nodes and channel regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If dual-sidewall floating gates are formed adjacent to a word line to increase device integration, then device integration is improved, but the operations are limited to 2-bit mode and word line width reduction is limited to suppress short channel effect
Solution Approach 1:
The invention divides the storage function into multiple independent storage nodes (first storage node and second storage node) positioned at different locations relative to the same word line and bit line. This segmentation allows each storage node to independently store 1 bit of data, enabling 2-bit operation modes while maintaining device integration through shared word line and bit line structures.
Solution Approach 2:
The invention transitions from planar floating gate structures to vertically positioned storage nodes located at different depths or positions relative to the word line. By positioning storage nodes in different spatial dimensions (e.g., one above and one below the word line, or at different vertical levels), the device achieves multi-bit operation without increasing the planar footprint, thus improving integration while enabling versatile operation modes.
2Adaptability or versatility
If planar-type transistor structure is used to perform multi-bit operations by locally storing electric charge, then multi-bit operations are enabled, but the short channel effect cannot be effectively suppressed and control gate length cannot be reduced
Solution Approach 1:
The invention moves away from planar transistor structures to a configuration where storage nodes are positioned in three-dimensional space relative to the word line and channel. By placing storage nodes at different vertical positions or locations, the device achieves multi-bit operation capability while maintaining effective control over the channel, thereby suppressing the short channel effect even with reduced control gate length.
Solution Approach 2:
The invention applies different functional regions within the transistor structure - storage nodes are locally positioned at specific locations (e.g., above and below the word line or at different channel positions) to enable multi-bit operations. This local differentiation allows multi-bit functionality without requiring a full planar structure, enabling better control over channel length and suppression of short channel effects in specific regions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables multi-bit and multi-level operations with increased device integration and reduced short channel effects, enhancing the capacity and speed of memory devices beyond traditional limitations.
Implementation Method 1
storage nodes between the gate electrodes and the fins, and insulated from the gate electrodes and the semiconductor substrate
Implementation Method 2
a semiconductor substrate, doped with impurities of a first conductivity type
Implementation Method 3
The flash memory operates by forming a conductive channel, i.e. a current flow, in a semiconductor substrate using induced change in threshold voltage which in turn corresponds to electric charge stored in the floating gate
Data Source
AI summary
In a non-volatile memory device allowing multi-bit and/or multi-level operations, and methods of operating and fabricating the same, the non-volatile memory device comprises, in one embodiment: a semiconductor substrate, doped with impurities of a first conductivity type, which has one or more fins defined by at least two separate trenches formed in the substrate, the fins extending along the substrate in a first direction; pairs of gate electrodes formed as spacers at sidewalls of the fins, wherein the gate electrodes are insulated from the semiconductor substrate including the fins and extend parallel to the fins; storage nodes between the gate electrodes and the fins, and insulated from the gate electrodes and the semiconductor substrate; source regions and drain regions, which are doped with impurities of a second conductivity type, and are separately formed at least at surface portions of the fins and extend across the first direction of the fins; and channel regions corresponding to the respective gate electrodes, formed at least at surface regions of the sidewalls of the fins between the source and the drain regions.