Multi-Bit Operation Cells With Resistance Calibration
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Solution Overview
Problem
Existing neural network operations, particularly multiply-accumulate (MAC) operations, face inefficiencies in processing multi-bit inputs and weights, and there is a need for improved hardware architectures to enhance efficiency and accuracy.
Innovation Solution
A multi-bit operation device comprising multi-bit cells with a memory to store weight resistance, a current source to generate weight voltage, multiplexers to output weight and fixed voltages, capacitors to generate charge data, and a switch for weight calibration, which converts analog sum data into digital data and calibrates weight resistances to improve accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If weight resistance is used for multi-bit operations in neural networks, then processing efficiency is improved, but calculation accuracy deteriorates due to resistance value errors
Solution Approach 1:
The patent applies preliminary calibration to measure and compensate for resistance value errors before performing neural network calculations. The calibration module measures the actual resistance values of weight resistors and stores correction values, which are then used to adjust subsequent calculations, thereby eliminating the impact of resistance errors on calculation accuracy while maintaining processing efficiency
Solution Approach 2:
The patent implements a feedback mechanism where the actual resistance values are measured and used to generate correction values that feed back into the calculation process. This feedback loop continuously compensates for resistance variations, ensuring accurate results while preserving the high-speed parallel processing capabilities of the resistance-based architecture
2Measurement precision
If calibration operations are performed to improve accuracy, then calculation precision is improved, but processing time increases
Solution Approach 1:
The calibration operation is performed once in advance to measure resistance values and generate correction values, which are then stored for use in subsequent calculations. This preliminary action separates the time-consuming calibration step from the actual neural network processing, allowing accurate calculations to be performed quickly without repeated calibration overhead
Solution Approach 2:
The system dynamically adjusts between calibration mode and calculation mode. During normal operation, the stored correction values are applied without performing new calibration measurements, thereby maintaining high processing speed. Calibration is only performed when needed, creating a dynamic balance between accuracy maintenance and processing efficiency
3Productivity
If multi-bit operations are implemented using existing hardware, then processing capability is improved, but power consumption increases
Solution Approach 1:
The patent replaces traditional digital computing mechanisms with a physics-based resistance computation system. By using the natural electrical properties of weight resistors to perform multiply-accumulate operations directly in the analog domain, the system achieves high processing capability with lower power consumption compared to conventional digital hardware that would require multiple sequential operations
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances the efficiency and accuracy of neural network operations by accurately calibrating weight resistances, reducing MAC calculation errors, and optimizing power consumption.
Implementation Method 1
a memory configured to store a weight resistance corresponding to a multi-bit weight
Implementation Method 2
a current source configured to apply current to the memory such that a weight voltage is generated from the weight resistance
Implementation Method 3
a plurality of capacitors connected respectively to the plurality of multiplexers and each configured to store a separate weight capacitance and generate charge data
Data Source
AI summary
A multi-bit operation device includes a plurality of multi-bit cells, and a converter configured to convert second sum data into digital data, wherein the second sum data is generated by summing pieces of first sum data output from each of the plurality of multi-bit cells, and each of the plurality of multi-bit cells comprises a memory configured to store a weight resistance corresponding to a multi-bit weight, a current source configured to apply current to the memory such that a weight voltage is generated from the weight resistance, a plurality of multiplexers connected to one another in parallel and connected to the memory in series and each configured to output a signal of one of the weight voltage and a first fixed voltage, based on a multi-bit input, a plurality of capacitors connected respectively to the plurality of multiplexers and each configured to store a separate weight capacitance and generate charge data by performing an operation on the output signal and the weight capacitance, a bit line configured to output first sum data generated by summing pieces of charge data generated by each of the plurality of capacitors, and a switch of which an end is connected to the memory and an opposite end to the end is connected to the bit line.