Multi-bit Programming Apparatus Optimizing Threshold Voltage Distribution
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Solution Overview
Problem
Multi-level cell (MLC) memory devices face challenges in improving storage density and reliability due to increased bit error rates and complexity of error correction codes (ECC) as the number of bits stored in a single memory cell increases, leading to difficulties in maintaining low bit error rates and optimizing threshold voltage distribution within a limited voltage window.
Innovation Solution
A new multi-level programming scheme that generates 2N threshold voltage states based on a target bit error rate (BER) for each page programming operation, assigns these states to N-bit data, and programs them in multi-bit cells using Fowler-Nordheim tunneling, thereby optimizing the distribution of threshold voltages and reducing the complexity of ECC implementation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of bits stored in a single memory cell increases, then storage density is improved, but bit error rate increases and reliability deteriorates
Solution Approach 1:
The patent segments the threshold voltage window into multiple distinct regions, each representing a stable voltage state. By carefully controlling the positioning and spacing of these regions within the voltage window, the system achieves both high storage density (storing multiple bits per cell) and low bit error rates (clear separation between states reduces misreading)
Solution Approach 2:
The patent optimizes the threshold voltage distribution by adjusting the positions and widths of voltage regions. This parameter optimization ensures that each voltage region is sufficiently separated from others to minimize read errors, while still fitting enough regions within the voltage window to achieve high storage density
2Quantity of substance
If the number of bits stored in a single memory cell increases, then storage density is improved, but the complexity of error correction codes increases
Solution Approach 1:
The patent prevents errors before they occur by creating well-separated, stable voltage regions during programming. This proactive approach to error prevention reduces the need for complex post-read error correction, as the physical design already minimizes error susceptibility
3Area of stationary object
If the voltage window for a memory cell is limited, then device integration is constrained, but the difference in threshold voltage between adjacent bits decreases as the number of bits increases
Solution Approach 1:
The patent applies different characteristics to different parts of the voltage window by creating regions with varying widths and positions. Each region is locally optimized to provide sufficient separation from adjacent regions while maximizing the use of the available voltage window, thereby maintaining adequate threshold voltage differences even as the number of bits increases
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the maximum bit error rate (BER) for each page, equalizes BER across pages, and optimizes the threshold voltage distribution within the voltage window, making all pages evenly reliable without the need for separate data interleaving or deinterleaving methods.
Implementation Method 1
programs them in multi-bit cells using Fowler-Nordheim tunneling
Data Source
AI summary
A multi-bit programming apparatus may include a first control unit that may generates 2N threshold voltage states based on a target bit error rate (BER) of each of the page programming operations, a second control unit that may assign any one of the threshold voltage states to the N-bit data, and a programming unit that may program the assigned threshold voltage state in each of the at least one multi-bit cell to program the N-bit data.