Drain-Programmed ROM Decoder for Multi-Bit Sensing and Low Leakage
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Solution Overview
Problem
Existing mask-programmable read-only memories (ROMs) face challenges in achieving high density and efficient power consumption due to layout constraints that necessitate source programming, leading to increased leakage currents and reduced storage efficiency.
Innovation Solution
Implementing a decoder for a read-only memory that utilizes a first and second logic circuit to process bit line voltages during different sensing phases, allowing for drain-programmed transistors that encode multiple bits per transistor, reducing semiconductor area and minimizing leakage currents.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If source-programmed MOSFETs are used in traditional mask-programmable ROMs, then the memory can be manufactured with conventional processes, but the memory density is limited and leakage current cannot be reduced
Solution Approach 1:
The patent inverts the traditional source-programming approach by using drain-programmed MOSFETs. Instead of programming the source connection to ground, the drain connection to the bit line is programmed. This inversion eliminates gate-induced drain leakage currents while enabling higher memory density through more efficient bit line sharing.
Solution Approach 2:
The patent changes the programming parameter from source connection state to drain connection state. By programming whether the drain is connected to the bit line or not, the system achieves both reduced leakage current and increased memory density through optimized transistor configuration and bit line sharing.
2Quantity of substance
If multiple transistors share bit lines to increase density, then memory density improves, but the complexity of decoding and sensing increases
Solution Approach 1:
The patent segments the sensing process into distinct phases (first sensing phase and second sensing phase) where different ground lines are activated. This segmentation allows multiple transistors to share bit lines while maintaining simple decoding logic, as each phase independently senses one bit without requiring complex multi-bit decoding circuits.
Solution Approach 2:
The patent employs periodic sensing phases where ground lines are alternately activated. During the first sensing phase, a first ground line is active while a second ground line is inactive, and vice versa during the second sensing phase. This periodic action enables multiple transistors to share bit lines with simple decoding, as each phase independently processes one bit.
3Ease of manufacture
If traditional mask-programming methods are used, then manufacturing processes are simple, but layout constraints limit further density improvement
Solution Approach 1:
The patent inverts the traditional source-programming approach to drain-programming, which maintains compatibility with conventional mask-programming manufacturing processes while achieving superior memory density. The inversion allows for more efficient bit line sharing and reduced leakage current without complicating the manufacturing process.
Data Source
AI summary
A drain programmed read-only memory includes a plurality of bit lines for each drain-programmed transistor. In addition, the drain-programmed read-only memory includes a pair of ground lines for each drain-programmed transistor. A decoder decodes a plurality of bits from each drain-programmed transistor by determining which bit line (if any) and which ground line is coupled to the drain-programmed transistor.