Multi-Bit Scan Chain Segmentation for Precise Defect Diagnosis
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Solution Overview
Problem
Existing scan techniques for integrated circuits with multi-bit flip-flops are inadequate as they limit diagnostic resolution, failing to accurately identify defects within multi-bit cells, leading to incomplete testing of integrated circuits.
Innovation Solution
A scan chain configuration with multi-bit cells and multiplexers that allow flexible diagnostic resolution, enabling precise identification of defect locations by selectively bypassing subsets of cell stages using controlled chain test patterns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multi-bit flip-flops are used to increase storage capacity, then the number of gates per chip increases, but the diagnostic resolution decreases and defect identification becomes inaccurate
Solution Approach 1:
The multi-bit flip-flop is segmented into multiple single-bit flip-flops, each with its own scan chain. This allows independent testing of each bit position, restoring diagnostic resolution to the single-bit level while maintaining the multi-bit storage capacity. The segmentation enables precise identification of which specific bit is defective rather than treating the entire multi-bit cell as a single unit.
2Ease of manufacture
If standard test vectors are used for core cells, then testing can be performed, but internal connections between cells become inaccessible and testing completeness deteriorates
Solution Approach 1:
Scan chains are introduced as intermediary structures that provide access to internal connections between core cells. The scan chains allow test vectors to be shifted into the internal flip-flops and for test responses to be shifted out, making previously inaccessible internal connections available for testing while maintaining compatibility with standard test vectors.
Data Source
AI summary
A circuit includes a scan chain comprising a cell structure, wherein the cell structure comprises a first plural number (N) of stages, and each of the stages is configured to store a bit. The circuit includes a second plural number(S) of multiplexers operatively coupled to the scan chain, wherein the S is determined as N/M, where the M represents a diagnostic resolution. The multiplexers are each configured to receive a respective one of S control signals to selectively bypass a corresponding subset of the stages.