Multi BLCS for Multi-State Verify in QLC NAND Flash
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Solution Overview
Problem
In QLC NAND flash memory, the increased programming time due to numerous verify steps required for programming four bits per cell leads to inefficiencies in data storage operations.
Innovation Solution
A sense circuit with multiple voltage clamps and data latches is connected to the bit line, allowing for different voltage biases to be applied simultaneously to reduce the number of verify operations, thereby reducing programming time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple verify steps are performed for programming four bits per cell in QLC NAND flash memory, then data storage capacity is improved, but programming time increases significantly
Solution Approach 1:
The patent segments the bit line voltage control into multiple discrete voltage levels (first through fourth clamp voltages) using separate voltage clamps. Each voltage level corresponds to different verify operation requirements, allowing simultaneous execution of multiple verify steps at different voltage biases without interference, thereby reducing total programming time while maintaining QLC capacity
Solution Approach 2:
The patent dynamically switches between different bit line voltage levels during the programming process. By using data latch transistors to selectively enable different voltage clamps, the system can transition between verify operations at different voltage biases, enabling flexible and efficient multi-state verification that reduces overall programming duration
2Productivity
If multiple voltage biases are applied to reduce verify operations, then programming efficiency is improved, but device complexity increases
Solution Approach 1:
The patent implements multi-functional voltage clamps that can operate at different voltage levels (first through fourth clamp voltages) using the same basic clamp circuit structure. Each clamp can serve multiple verify operations at different voltage biases, reducing the need for entirely separate circuits for each verify step and thereby limiting the increase in overall device complexity
Solution Approach 2:
The patent introduces data latch transistors as intermediary control elements that manage the selection and switching between different voltage clamps. These latch transistors act as mediators between the control logic and the multiple voltage clamps, simplifying the control architecture by providing a unified interface for managing multiple voltage biases without requiring complex direct control circuitry
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in a significant reduction in the number of verify operations, specifically achieving a fifty percent or more reduction, enhancing the efficiency of programming in QLC memory devices.
Implementation Method 1
the first voltage clamp configured to limit the bit line voltage to a first clamp voltage; a second voltage clamp disposed on the bit line, the second voltage clamp configured to limit the bit line voltage to a second clamp voltage
Data Source
AI summary
An apparatus and method for a multi-state verify of a memory array are provided. A sense circuit of a memory device is connected to a bit line of the memory array. The sense circuit includes a first voltage clamp, a second voltage clamp, and a program data latch disposed on the bit line. The first and second voltage clamps are biased to first and second voltages, respectively, where the first voltage is lower than the second voltage. When a high bias is applied to the program data latch, the program data latch is in an OFF state, and the first voltage clamp limits the bias on the bit line to the first voltage. When a low bias is applied to the program data latch, the program data latch is in an ON state, and the second voltage clamp limits the bias on the bit line to the second voltage.