Multi-Block Circuit Design with Unique Net Identification
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Solution Overview
Problem
During integration automated testing of multi-block circuits, challenges arise in uniquely identifying components and nets with identical designators, and in handling external nets connecting components from different blocks, which complicates electrical simulation and schematic verification.
Innovation Solution
A method and apparatus for generating a description of a merged block that assigns unique designators to components and nets, incorporating original block designators and references, allowing for the creation of a virtual block that simulates the combined functionalities of multiple blocks, enabling unique identification and testing of interconnected blocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If blocks are merged for integration testing, then connectivity verification and electrical simulation can be performed, but components and nets with identical designators across blocks cannot be uniquely identified
Solution Approach 1:
The patent divides the identification system into two levels: block-level designators (identifying the block) and component-level designators (identifying the component within the block). This segmentation allows unique identification of components across merged blocks by combining both levels of identification, resolving the ambiguity of identical designators in different blocks.
Solution Approach 2:
The patent adds a new dimension to component identification by introducing block-level context. Instead of relying solely on component designators (0D), the system incorporates block identifiers (1D), creating a hierarchical identification structure that enables unique differentiation of components with identical designators across different blocks.
2Reliability
If external nets are handled separately for each block, then connectivity can be maintained, but the complexity of electrical simulation and schematic verification increases
Solution Approach 1:
The patent merges external nets from multiple blocks into a unified net representation during the block merging process. This consolidation maintains connectivity information while reducing the complexity of electrical simulation and schematic verification by eliminating redundant external net handling across blocks.
Solution Approach 2:
The patent creates a universal net representation that serves multiple functions: it maintains connectivity between blocks, provides unique identification across merged blocks, and simplifies electrical simulation. This multi-functional approach reduces the need for separate handling of external nets in different blocks.
3Productivity
If automatic merging of blocks is implemented, then design time is reduced, but handling of identical designators becomes problematic
Solution Approach 1:
The patent performs preliminary action by automatically generating unique designators before the actual merging process. The system pre-establishes a naming convention that incorporates block identifiers, ensuring that components with identical designators in different blocks receive differentiated designators during the automated merging process.
Solution Approach 2:
The patent implements feedback mechanisms during automated merging to detect and resolve designator conflicts. When identical designators are detected across blocks, the system automatically applies differentiation rules based on block identifiers, providing feedback that ensures unique identification while maintaining automation efficiency.
Data Source
AI summary
A method, system and computer program product, the method comprising: obtaining information of a circuit to be designed comprising two blocks, the information comprising: block components of the two blocks, information of connectors connecting the two blocks, information of a plurality of internal nets, each internal net connecting components within a same block, information of a plurality of external nets, each external net connecting a component to a connector; automatically generating a design of a merged block, the design comprising: a plurality of circuit components, comprising circuit components of the first block and the second block, each circuit component having a unique designator and an association to an original component; a plurality of internal circuit nets comprising a plurality of internal nets, each internal net associated with a unique designator and an association to a respective internal net designator, and a plurality of combined circuit nets based on the plurality of external nets, each external net connecting a component from the first block and a component from the second block; testing the design of the circuit based; and outputting results of the testing.