Multi-Block Memory Read Current Management
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The read operation in memory devices, particularly during multi-block operations in computing-in-memory (CIM) or in-memory-searching (IMS) applications, results in a large constant current, which poses challenges for power management systems.
Innovation Solution
The implementation of forward voltage read and reverse voltage read techniques in memory devices, which involve specific circuitry configurations to manage bit line capacitors and sense voltage threshold levels of memory cells, thereby reducing current consumption during multi-block operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multi-block read operation is performed in memory devices, then data reading capability is improved, but current consumption increases
Solution Approach 1:
The patent implements periodic action by dividing the read operation into distinct phases: a precharge phase where the bit line is charged to a reference voltage level, and a sense phase where the actual reading occurs. This periodic charging and discharging allows the memory device to perform multi-block read operations efficiently while controlling current consumption through timed voltage application rather than continuous current flow
Solution Approach 2:
The patent applies preliminary action by precharging the bit line to a reference voltage level before the actual read operation begins. This precharge phase prepares the circuitry in advance, ensuring that when the read operation commences, the necessary voltage conditions are already established, thereby reducing the peak current demand during the critical sensing phase
2Reliability
If constant current is used during read operation, then reading stability is improved, but power system pressure increases
Solution Approach 1:
The patent implements parameter changes by dynamically adjusting the voltage level on the bit line between different operational phases. During the precharge phase, the bit line is charged to a reference voltage level, and during the sense phase, the voltage changes based on the memory cell states being read. This dynamic voltage modulation maintains reading stability through controlled parameter transitions while avoiding the continuous high current demand of constant current operation
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
These techniques effectively limit current consumption during multi-block read operations, reducing the pressure on power systems and enhancing the efficiency of memory device operations.
Implementation Method 1
detecting a voltage level of the discharged capacitor
Data Source
AI summary
Systems, methods, circuits, and apparatus for managing multi-block operations in memory devices are provided. In one aspect, a memory device includes a memory cell array including at least two blocks, a bit line coupled to a string of memory cells in each of the at least two blocks respectively, a common source line (CSL) coupled to strings coupled to the bit line in the at least two blocks, and a circuitry configured to perform a multi-block operation in the memory cell array by at least one of: forming a first current path from the bit line through the strings to the CSL coupled to a ground to discharge a capacitor associated with the bit line that is pre-charged, or forming a second current path from the CSL coupled to a supply voltage through the strings to the bit line to charge the capacitor that is pre-discharged.