Multi-Bridge Channel Transistor Structure for Reduced Gate Leakage
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Solution Overview
Problem
As semiconductor devices become highly integrated, the reduced separation distance between source/drain layers of transistors leads to deteriorated electrical characteristics.
Innovation Solution
A semiconductor device design featuring vertically stacked channels with specific distance and thickness configurations, including an active pattern, insulation pattern, and gate structure, which reduces leakage current and enhances electrical performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the separation distance between source/drain layers is reduced to achieve high integration, then device density increases, but electrical characteristics deteriorate due to increased leakage current
Solution Approach 1:
The gate structure is segmented into multiple gates (first gate and second gate) that are positioned at different heights and angles. This segmentation allows each gate to independently control different regions of the channel, providing precise control over leakage current while maintaining high integration density. The multi-bridge channel structure is also segmented into multiple channels spaced apart, enabling independent control of electrical characteristics.
Solution Approach 2:
The invention transitions from a planar gate structure to a three-dimensional multi-bridge channel structure with gates positioned at different vertical levels and angular orientations. This dimensional change enables better control over the electric field distribution and leakage current paths without increasing the footprint area, thus maintaining high integration while improving electrical characteristics.
2Quantity of substance
If channel spacing is reduced to increase channel density, then device capacity increases, but gate-channel leakage current increases
Solution Approach 1:
Different regions of the gate structure have different properties - the first gate and second gate are positioned at different heights and angles, creating locally optimized electric field distributions. The insulation patterns are selectively placed in specific regions to provide localized leakage current blocking, allowing high channel density while controlling leakage in critical areas.
Solution Approach 2:
Insulation patterns are introduced as intermediary elements between the gates and channels, and between adjacent channels. These insulation patterns act as mediators that block leakage current paths while allowing the channels to remain closely spaced for high density. The insulation patterns are strategically positioned to interrupt harmful current paths without affecting the desired current flow through channels.
Data Source
AI summary
A semiconductor device is provided. The semiconductor device includes: an active pattern provided on a substrate having an upper surface; an insulation pattern provided above the substrate and contacting an upper surface of the active pattern; channels spaced apart from each other along a direction perpendicular to the upper surface of the substrate, each of the channels including a material provided in the active pattern; and a gate structure contacting an upper surface of the insulation pattern, an upper surface of the channels, a lower surface of the channels, and sidewalls of the channels opposite to each other. A first distance between an upper surface of the active pattern and a lowermost one of the channels is greater than a second distance between an upper surface of one of the channels and a lower surface of an adjacent channel.