Multi-bridge Channel Transistor Source/Drain Stress Engineering

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Solution Overview

Problem

Existing semiconductor devices face challenges in enhancing the performance and reliability of multi-gate transistors, particularly in applying uniform compressive stress to the multi-channel active pattern to improve hole mobility.

Innovation Solution

The semiconductor device incorporates an active pattern with a lower pattern and multiple sheet patterns, a gate structure surrounding the sheet patterns, and a source/drain pattern with specific semiconductor patterns that apply compressive stress uniformly across the channel region.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If multi-gate transistor structure is used to enhance current control capability, then device performance is improved, but applying uniform compressive stress to the multi-channel active pattern becomes difficult

Engineering Contradiction:
Improvedevice performanceVSAvoiduniform compressive stress application
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The source/drain pattern is segmented into multiple semiconductor patterns (first, second, third, and fourth semiconductor patterns) positioned at different locations. Each pattern can be independently designed with specific thicknesses and positions to apply compressive stress uniformly across different sheet patterns of the multi-channel active pattern, resolving the difficulty of applying uniform stress to the complex multi-gate structure.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different semiconductor patterns are assigned different thicknesses (e.g., third semiconductor pattern has greater thickness than first and second patterns) and different positions (first pattern contacts lower pattern, fourth pattern fills source/drain recess). This local variation in geometry allows each pattern to apply compressive stress to specific regions of the multi-channel active pattern, achieving uniform overall stress distribution.

Inventive Principle:
Principle #3Local quality

2Reliability

If germanium doping is increased to enhance hole mobility, then electrical characteristics improve, but structural uniformity and manufacturing precision become more challenging

Engineering Contradiction:
Improvehole mobilityVSAvoidstructural uniformity
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The source/drain structure is divided into multiple semiconductor patterns that can be independently doped with germanium. This segmentation allows precise control of doping concentration in each pattern, enabling high hole mobility through germanium doping while maintaining structural uniformity through independent optimization of each pattern's doping level and geometry.

Inventive Principle:
Principle #1Segmentation

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration enhances the electrical characteristics of the semiconductor device by applying uniform compressive stress, thereby improving hole mobility and device performance.

Implementation Method 1

applying uniform compressive stress to the multi-channel active pattern to improve hole mobility

Methodology Applied
Scientific EffectCompressive stress: Compression

Data Source

PatentUS12289908B2Semiconductor device having multi-bridge channel field-effect transistor including source/drain pattern with a plurality of semiconductor patterns
Publication Date: 2025.04.29 SAMSUNG ELECTRONICS CO LTD
  • US12289908B2 patent drawing
  • US12289908B2 patent drawing
  • US12289908B2 patent drawing

AI summary

A semiconductor device includes an active pattern including a lower pattern and a plurality of sheet patterns; a gate structure disposed on the lower pattern and surrounding the plurality of sheet patterns; and a source/drain pattern filling a source/drain recess formed on one side of the gate structure. The source/drain pattern includes a first semiconductor pattern extending along the source/drain recess and contacting the lower pattern, a second and third semiconductor patterns sequentially disposed on the first semiconductor pattern, a lower surface of the third semiconductor pattern is disposed below a lower surface of a lowermost sheet pattern, a side surface of the third semiconductor pattern includes a planar portion, and a thickness of the second semiconductor pattern on the lower surface of the third semiconductor pattern is different from a thickness of the second semiconductor pattern on the planar portion of the side surface of the third semiconductor pattern.