Multi-Bridge Channel FET Gate Layout for Lower Leakage Current
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Solution Overview
Problem
The reduced separation distance between source/drain layers in semiconductor devices leads to deteriorated electrical characteristics.
Innovation Solution
A semiconductor device design with vertically stacked channels and a specific gate structure configuration that includes an insulation pattern and gate structure with varying thicknesses and distances to reduce leakage current, enhancing electrical performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the separation distance between source/drain layers is reduced to achieve higher integration, then device density increases, but electrical characteristics deteriorate due to increased leakage current
Solution Approach 1:
The gate structure is segmented into multiple gates (first gate and second gate) positioned at different heights, with each gate controlling specific channel regions. This segmentation allows independent optimization of different channel portions, enabling reduced source/drain separation while maintaining electrical control and reducing leakage current through selective gating.
Solution Approach 2:
The invention transitions from a planar gate structure to a three-dimensional stacked configuration where gates are arranged vertically at different heights. This dimensional change enables the gate to contact channels from multiple levels, providing enhanced control over the channel region and effective leakage suppression even with reduced horizontal separation distance between source/drain layers.
2Ease of manufacture
If a uniform gate structure is used across all channels, then manufacturing is simplified, but leakage current cannot be effectively reduced due to varying channel characteristics
Solution Approach 1:
Different gate regions are designed with different thicknesses and positions to match local channel characteristics. The first gate and second gate have different dimensions and are positioned at different heights, allowing each gate portion to be optimized for its specific channel region. This local optimization effectively reduces leakage current while maintaining manufacturability through standard deposition processes.
Solution Approach 2:
The gate structure employs varying parameters including different gate thicknesses, different positions relative to channels, and different materials for first and second gates. These parameter variations enable tailored control of different channel regions, addressing leakage current issues without requiring complex non-uniform fabrication processes.
Data Source
AI summary
A semiconductor device is provided. The semiconductor device includes: an active pattern provided on a substrate having an upper surface; an insulation pattern provided above the substrate and contacting an upper surface of the active pattern; channels spaced apart from each other along a direction perpendicular to the upper surface of the substrate, each of the channels including a material provided in the active pattern; and a gate structure contacting an upper surface of the insulation pattern, an upper surface of the channels, a lower surface of the channels, and sidewalls of the channels opposite to each other. A first distance between an upper surface of the active pattern and a lowermost one of the channels is greater than a second distance between an upper surface of one of the channels and a lower surface of an adjacent channel.