Multi-Bridge Channel FET Structure for High-Density Reliable Switching
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Solution Overview
Problem
The reduction in size of planar MOSFETs leads to limitations in operation properties, necessitating the development of semiconductor devices with improved integration density and electrical properties, such as FinFETs and gate-all-around field-effect transistors.
Innovation Solution
A semiconductor device design featuring a substrate with active regions, multiple channel layers surrounded by gate electrodes, insulating isolation patterns, and epitaxial layers on channel side surfaces, enhancing electrical properties and reliability through a multi-bridge channel FET structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If planar MOSFET size is reduced to increase integration density, then integration density is improved, but operation properties deteriorate
Solution Approach 1:
The patent transitions from planar 2D channel structure to three-dimensional FinFET structure with vertical fins extending from the substrate. This dimensional change allows the channel to be controlled from multiple directions (gate-all-around configuration), maintaining effective gate control and carrier transport properties even as the device footprint is reduced, thereby preserving operation properties while increasing integration density.
Solution Approach 2:
The gate electrode completely surrounds the channel region in a nested configuration, with the gate wrapping around the vertical fin structure. This gate-all-around configuration provides 360-degree control of the channel, ensuring reliable operation properties while enabling smaller device dimensions and higher integration density.
2Reliability
If channel length is increased to improve electrical signal transmission, then electrical properties are improved, but device area increases
Solution Approach 1:
The channel is extended in the vertical dimension through FinFET fins rather than only in the horizontal plane. The effective channel length is achieved through the vertical fin height and perimeter, allowing improved electrical signal transmission without proportionally increasing the planar device footprint, thus maintaining compact device area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design improves electrical signal transmission and reliability by lengthening the effective area and channel length, resulting in enhanced performance and functionality.
Implementation Method 1
epitaxial layers on side surfaces of the plurality of first channel layers and the plurality of second channel layers that respectively oppose each other
Data Source
AI summary
A semiconductor device may include a substrate including an active region extending in a first direction; a device isolation layer defining the active region; first and second gate electrodes extending in a second direction and spaced apart from each other; first channel layers apart from each other and surrounded by the first gate electrode; second channel layers apart from each other and surrounded by the second gate electrode; an insulating isolation pattern between the first and second gate electrodes and between the first and second channel layers; gate dielectric layers between the first channel layers and the first gate electrode and between the second channel layers and the second gate electrode; and epitaxial layers on opposing side surfaces of the first and second channel layers. Portions of the epitaxial layers may overlap the insulating isolation pattern, gate dielectric layers, and first and second gate electrodes in a third direction.