Multi-Bridge Gate Capping Layout for Recess Variation Control
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Solution Overview
Problem
Semiconductor devices with multi-gate transistors face issues such as recess variation, metal climbing, and dishing, which affect their density and performance.
Innovation Solution
The semiconductor device design includes a substrate with active patterns, gate structures, and capping patterns that surround sheet patterns, along with a gate spacer and etching stop film, to improve element performance and reliability by controlling the layout and coverage of these components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multi-gate transistor is implemented to increase device density, then device density is improved, but recess variation and metal climbing occur
Solution Approach 1:
The gate structure is divided into multiple segments including a first gate electrode, second gate electrode, first gate capping pattern, and second gate capping pattern. These segmented components are arranged in a multi-bridge channel configuration, allowing independent optimization of each segment to reduce recess variation while maintaining high device density.
Solution Approach 2:
Different capping patterns are applied to different regions of the gate structure. The first gate capping pattern is positioned at a first height and the second gate capping pattern at a second height, creating local quality variations that control metal climbing in specific areas while maintaining overall device performance.
2Productivity
If multi-gate transistor is implemented to increase device density, then device density is improved, but metal climbing occurs
Solution Approach 1:
The gate structure is divided into multiple segments including a first gate electrode, second gate electrode, first gate capping pattern, and second gate capping pattern. These segmented components are arranged in a multi-bridge channel configuration, allowing independent optimization of each segment to reduce recess variation while maintaining high device density.
Solution Approach 2:
Different capping patterns are applied to different regions of the gate structure. The first gate capping pattern is positioned at a first height and the second gate capping pattern at a second height, creating local quality variations that control metal climbing in specific areas while maintaining overall device performance.
3Reliability
If gate structure surrounds sheet patterns to improve performance, then element performance is improved, but device complexity increases
Solution Approach 1:
The gate structure is divided into multiple segments including a first gate electrode, second gate electrode, first gate capping pattern, and second gate capping pattern. These segmented components are arranged in a multi-bridge channel configuration, allowing independent optimization of each segment to reduce recess variation while maintaining high device density.
Solution Approach 2:
The gate structure employs a nested configuration where gate electrodes and gate capping patterns are arranged in multiple layers surrounding the sheet patterns. The first gate capping pattern is positioned at a first height and the second gate capping pattern at a second height, creating a nested structure that improves element performance while managing complexity through systematic layering.
Data Source
AI summary
A semiconductor device includes a substrate, an active pattern including a lower pattern extending in a first direction and a plurality of sheet patterns above an upper surface of the lower pattern and spaced apart from the lower pattern in a second direction substantially perpendicular to the first direction, a gate structure on the lower pattern and including a gate electrode and a gate insulating film, the gate electrode and the gate insulating film at least partially surrounding the plurality of sheet patterns, a first gate capping pattern on the gate structure and above the plurality of sheet patterns in the second direction, a gate spacer extending along a side wall of the gate structure, and a second gate capping pattern extending along an upper surface of the gate structure and an upper surface of the first gate capping pattern.