Multi-Buffer Boot Code Load System for Server Sockets
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Solution Overview
Problem
In multi-CPU socket systems, the increasing firmware size and lack of cross-socket coherency during the boot process lead to interface contention and delays due to the Serial Peripheral Interface (SPI) limitations, causing prolonged boot times as each CPU fetches and runs the same boot code independently.
Innovation Solution
Implementing a multi-buffer system where one CPU loads and executes boot code, allowing other CPUs to access and copy segments from memory buffers, reducing the boot code fetch over the link and leveraging spatial locality to minimize bandwidth usage and optimize boot times.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If each CPU socket fetches boot code independently via SPI interface, then each CPU can execute boot code autonomously, but the SPI interface experiences contention and boot time increases
Solution Approach 1:
The first CPU socket fetches and executes boot code in advance, setting up memory buffers before other CPUs need to access the same code. This preliminary action allows subsequent CPUs to retrieve code from already-loaded buffers rather than fetching from storage, dramatically reducing boot time while maintaining autonomous execution capability
Solution Approach 2:
Memory buffers serve as an intermediary between the SPI interface and CPU sockets. The first CPU loads boot code into these buffers via SPI, and subsequent CPUs access the code through the buffers rather than directly through SPI, eliminating interface contention while preserving autonomous boot execution
2Adaptability or versatility
If firmware size increases to support complex server CPU SoC, then functionality and features improve, but boot code fetch time and interface bandwidth requirements increase
Solution Approach 1:
The boot code fetch process is segmented into phases: the first CPU socket fetches code in segments and loads them into memory buffers, while subsequent CPUs access segments from buffers. This segmentation allows progressive loading and reduces the time any single CPU waits for complete firmware, accommodating larger firmware sizes without proportionally increasing boot time
Solution Approach 2:
Memory buffers are pre-loaded with boot code segments by the first CPU socket before other CPUs need to execute them. This preliminary action ensures that even as firmware size increases, the actual fetch operation is amortized across multiple CPUs and time periods, preventing linear increase in boot time
3Productivity
If multiple CPUs fetch the same boot code in parallel, then each CPU can boot independently, but SPI interface bandwidth is exceeded and contention occurs
Solution Approach 1:
The first CPU socket copies boot code from the SPI interface into memory buffers, and subsequent CPUs copy the same code from these buffers rather than fetching from the SPI interface. This copying mechanism reduces total data fetch volume from the SPI interface from 4 MB (in an 8-socket system) to approximately 1 MB, eliminating interface contention while preserving parallel boot capability
Solution Approach 2:
Multiple CPU sockets merge their boot code access through shared memory buffers. Instead of each CPU independently fetching code through the SPI interface, they combine their access patterns by reading from the same buffer memory, reducing the aggregate data volume on the SPI interface while maintaining independent execution
Data Source
AI summary
Examples described herein provide a hardware-software interface solution reads the boot code in segments into a buffer. A given boot code segment is stored in the buffer. A second buffer can be written-to with another boot code segment while the boot code segment in the buffer is read-from. A central processing unit (CPU) socket provides coordination such that one or more CPU sockets have copied the segment before permitting the segment to be overwritten in the buffer.