Multi-Buffer Cache Memory for Read Latency Reduction
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Solution Overview
Problem
Non-volatile memory devices, such as flash memory, suffer from high power consumption and slow operation speed, leading to significant read latency issues that can impact microprocessor performance, especially in multi-core systems where memory requests become non-sequential or interleaved.
Innovation Solution
Implementing a memory device structure with a memory array, cache memory, and multiple buffers that pre-fetch and store consecutive data lines, allowing for sequential output and reducing latency by maintaining data in buffers for subsequent read operations, thereby minimizing memory array access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If non-volatile memory devices are used to store data, then data retention and non-volatility are improved, but read latency and operation speed deteriorate
Solution Approach 1:
The patent implements a cache memory system that pre-loads and stores data lines from non-volatile memory into buffer structures before they are needed for processing. This preliminary action allows the system to have data ready in fast access memory, eliminating the need to wait for slow NVM access during actual read operations, thus reducing read latency while maintaining data retention benefits of NVM
Solution Approach 2:
The patent introduces cache memory and buffer structures as intermediary components between the slow non-volatile memory and the fast microprocessor. This intermediary layer provides a middle ground with faster access times than NVM but lower cost and capacity than full SRAM cache, resolving the speed-retention contradiction by mediating data transfer between the two memory types
2Speed
If cache memory and multiple buffers are implemented, then read latency is reduced, but device complexity increases
Solution Approach 1:
The patent divides the memory system into distinct segments: non-volatile memory array, cache memory, and multiple buffer structures (including data buffers and scratch pad buffers). This segmentation allows each component to be optimized for its specific function and enables parallel operation of multiple buffers, reducing read latency while managing complexity through modular organization
Solution Approach 2:
The patent introduces multiple buffers operating in parallel, effectively adding a temporal dimension to data access. By having multiple buffers that can be accessed simultaneously or in rapid succession, the system achieves faster effective access times without proportionally increasing the complexity of any single buffer structure
Data Source
AI summary
A memory device can include: a memory array arranged to store data lines; an interface that receives a first read command requesting bytes of data in a consecutively addressed order from a starting byte; a cache memory having a first buffer storing a first data line including the starting byte, and a second buffer storing a second data line, from the cache memory or the memory array; output circuitry that accesses data from the first buffer, and sequentially outputs each byte from the starting byte through a highest addressed byte of the first data line; and from the second buffer and sequentially outputs each byte from a lowest addressed byte of the second data line until the requested bytes of data have been output in order to execute the first read command, the contents of the first and second buffers being maintained in the cache memory.