Multi-Buffer Data Alignment for Ethernet Packet Transfer
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Solution Overview
Problem
The existing data transfer systems face bottlenecks due to latency from the main memory to the aligner, leading to inefficiencies in accommodating increasing network data transfer speeds, particularly in Ethernet communications, as they require sequential data input and cannot start transfers until the FIFO has free space, resulting in dead time and suboptimal bus usage.
Innovation Solution
A data transfer device with a plurality of buffer memories that can receive and provide data independently, a bus arbiter to control data bus usage, and a selector to align data from the buffer memories for packet communication, allowing for efficient alignment and transfer processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If data transfer waits for FIFO free space before starting, then data alignment sequence is maintained, but transfer speed decreases and dead time increases
Solution Approach 1:
The single FIFO buffer is divided into multiple FIFO buffers (first FIFO buffer and second FIFO buffer). Data can be stored in one buffer while another buffer's data is being processed, enabling parallel operations and eliminating the need to wait for a single buffer to clear, thus maintaining alignment while improving transfer speed.
Solution Approach 2:
Multiple FIFO buffers are prepared in advance, allowing the system to pre-fill one buffer while simultaneously processing data from another. This preliminary preparation eliminates waiting time and keeps the data transfer pipeline continuously full, improving productivity without compromising alignment.
2Reliability
If sequential data input is required for alignment, then packet communication integrity is maintained, but bus usage efficiency decreases
Solution Approach 1:
The data input process is segmented across multiple FIFO buffers, allowing the bus to service multiple buffers in parallel or sequence without idle waiting. While one buffer is being filled from the bus, another buffer's data can be simultaneously aligned and output, eliminating bus idle time while maintaining sequential integrity through controlled data selection.
Solution Approach 2:
The system maintains continuous useful action on the data bus by ensuring that while one FIFO buffer is being filled, another buffer's data is being processed. This continuous operation eliminates bus idle time and maximizes bus utilization while still producing sequentially aligned output through the selector mechanism.
3Device complexity
If single buffer is used for data storage, then system complexity is reduced, but data transfer latency increases
Solution Approach 1:
The single buffer is segmented into multiple FIFO buffers that can operate in parallel. This segmentation allows data to be stored and processed concurrently in multiple locations, reducing the time data waits to be processed while adding only moderate complexity through the use of additional buffer memory and a selector.
Solution Approach 2:
The system dynamically switches between multiple FIFO buffers based on their fill and processing states. The selector dynamically chooses which buffer to read from, allowing the system to adapt to varying data arrival patterns and maintain optimal throughput, reducing latency while managing complexity through dynamic control.
Data Source
AI summary
A communication data processing device according to an aspect of the invention includes a memory storing data, a data bus transmitting data read from the memory, a plurality of buffer memories temporarily storing data from the memory via the data bus and being capable of receiving and providing data independently of each other, a bus arbiter arbitrating use of the data bus to control data read from the memory to the plurality of buffer memories, an aligner aligning input data in a sequence corresponding to a packet communication, and a selector selecting a buffer memory from the plurality of buffer memories to output data from the selected buffer memory toward the aligner.