Multi-Bump Connection with Bent Redistribution Lines
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Solution Overview
Problem
As semiconductor technologies evolve, the increasing miniaturization of semiconductor chips and the integration of multiple device dies into larger packages pose challenges in manufacturing, requiring precise handling to reduce defects and effectively connect conductive features in interposers and package substrates.
Innovation Solution
The development of multi-bump bonding structures with bent redistribution lines that interconnect bumps to vias, where the vias are vertically offset from common metal pads, helps in redistributing stress and reducing the risk of line breaks and delamination by using a process involving multiple dielectric layers and metal plating processes to form conductive pads and traces.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple device dies are bonded together to form larger packages with more integrated functions, then the functionality and integration level improve, but the manufacturing complexity and defect risk increase
Solution Approach 1:
The interposer is divided into multiple dielectric layers (first dielectric layer, second dielectric layer) with separate via structures (first vias, second vias) and conductive trace layers. This segmentation allows independent formation and optimization of each layer, reducing manufacturing complexity while enabling high integration of multiple device dies.
Solution Approach 2:
The patent transitions from planar connections to three-dimensional vertical connections through vias extending through dielectric layers. The bent conductive traces provide additional dimensional flexibility, allowing connections to be routed around obstacles and accommodating thermal expansion differences between bonded dies.
2Length of moving object
If conductive features in interposers and package substrates are made smaller to support miniaturization, then the chip size reduction is achieved, but the manufacturing precision requirements increase
Solution Approach 1:
Conductive traces are formed in the dielectric layers before bonding the device dies to the interposer. This preliminary formation ensures that conductive features are already in place and properly aligned, reducing the precision requirements during the bonding process itself and enabling smaller chip sizes.
Solution Approach 2:
Multiple conductive trace layers are nested within the dielectric layers, with each layer providing additional interconnection pathways. This nested structure allows for redundant routing options and compensates for alignment tolerances, maintaining manufacturing feasibility even with smaller conductive features.
3Ease of manufacture
If straight conductive traces are used to connect bumps to vias, then the manufacturing process is simpler, but the stress concentration and line break risk increase
Solution Approach 1:
Conductive traces are designed with bent or curved geometries instead of straight lines. These bent traces distribute mechanical stress more evenly along their length and avoid stress concentration at sharp corners, significantly reducing the risk of line breaks while maintaining electrical connectivity.
Solution Approach 2:
The trace geometry parameters are changed from straight to bent configurations, and the trace width or thickness may be adjusted in different sections to optimize both stress distribution and electrical performance. This parameter optimization maintains manufacturing feasibility while improving reliability.
4Ease of manufacture
If vias are positioned directly over metal pads for direct alignment, then the manufacturing alignment is easier, but the stress distribution and delamination risk worsen
Solution Approach 1:
The via positions are deliberately offset from direct alignment with metal pads, creating an asymmetric configuration. This offset positioning allows bent conductive traces to connect the vias to the pads at angles, distributing mechanical stress more evenly and reducing delamination risk at the pad-via interface.
Solution Approach 2:
Bent conductive traces serve as intermediary elements between the vias and metal pads, providing a flexible connection that accommodates dimensional mismatches and distributes stress. These traces mediate the mechanical and electrical connection, reducing direct stress concentration at the via-pad interface.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively reduces the risk of defects by redistributing stress and ensuring reliable electrical connections in multi-bump bonding structures, enhancing the reliability and durability of semiconductor packages.
Implementation Method 1
A first conductive bump and a second conductive bump are bonded to a first conductive pad
Implementation Method 2
the first conductive trace electrically connects the first conductive pad to the first via, and the first conductive pad, the first conductive trace, and the first via form a continuous conductive region
Data Source
AI summary
A method includes forming a package component comprising forming a dielectric layer, patterning the dielectric layer to form an opening, and forming a redistribution line including a via in the opening, a conductive pad, and a bent trace. The via is vertically offset from the conductive pad. The conductive pad and the bent trace are over the dielectric layer. The bent trace connects the conductive pad to the via, and the bent trace includes a plurality of sections with lengthwise directions un-parallel to each other. A conductive bump is formed on the conductive pad.