Multi-Bus Memory Core Access Without CPU Arbitration
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Solution Overview
Problem
The existing semiconductor apparatuses with variable data width memory struggle to perform multiple data transfer operations simultaneously with multiple CPUs, leading to deterioration in data processing performance due to limited address signal routes, necessitating arbitration and increased complexity.
Innovation Solution
A semiconductor apparatus is designed with multiple bus-interface circuits, memory cores, and a select circuit that allows for independent access control signal selection, enabling each memory core to be accessed by a separate CPU without the need for arbitration, thus preventing performance degradation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single address signal route is used in memory, then the memory structure is simple, but multiple data transfer operations with multiple CPUs cannot be performed simultaneously
Solution Approach 1:
The patent divides the single address signal route into multiple separate routes, with each route dedicated to a specific CPU. This segmentation allows multiple CPUs to access the memory simultaneously without interference, resolving the contradiction between structural simplicity and transfer performance.
Solution Approach 2:
The patent introduces a new dimension of control by adding a select circuit that chooses which CPU's address signal is routed to the memory. This dimensional addition enables simultaneous access from multiple CPUs while maintaining a relatively simple base structure.
2Ease of operation
If arbitration circuit is used to manage multiple data transfer operations, then data transfer can be managed, but the circuit complexity increases and performance deteriorates
Solution Approach 1:
The patent extracts the arbitration function from a complex arbitration circuit and replaces it with a simple select circuit that directly routes address signals from different CPUs to the memory. This extraction maintains operational capability while dramatically reducing circuit complexity.
Solution Approach 2:
Instead of using an arbitration circuit to select which CPU can access the memory, the patent inverts the approach by providing dedicated routes for each CPU and using a select circuit to choose which route is active. This inversion eliminates the need for complex arbitration logic.
3Productivity
If multiple address signal routes are provided for multiple CPUs, then simultaneous data transfer operations are enabled, but the circuit congestion increases
Solution Approach 1:
The patent introduces a select circuit as an intermediary component that manages the routing of address signals from multiple CPUs to the memory. This intermediary enables simultaneous access while keeping the routing logic centralized and manageable, preventing circuit congestion.
Data Source
AI summary
A semiconductor apparatus according to an aspect of the present invention includes first and second bus-interface circuits, a first memory core connected to the first bus-interface circuit through a first data bus, the first memory core being connected to a first access control signal output from the first bus-interface circuit, a second memory core connected to the second bus-interface circuit through a second data bus, and a select circuit that selectively connects one of the first access control signal and a second access control signal output from the second bus-interface circuit to the second memory core.