Multi-Bus Memory Controller Architecture for Mass Storage SoC
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Solution Overview
Problem
Current memory controllers, particularly those using uni-bus architectures, face inefficiencies in data transfer between mass storage devices and host components, leading to increased time requirements due to shared bus usage and power consumption issues as data storage capacities grow.
Innovation Solution
Implementing a multi-bus architecture within the memory controller, comprising a controller first bus for executing code and a controller second bus for data transfer, utilizing Direct Memory Access (DMA) to isolate code from data and enable independent operation, thereby increasing data throughput and conserving power by reducing bus usage and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a uni-bus architecture is used in the memory controller, then device complexity is reduced, but data throughput is limited due to shared bus usage and congestion
Solution Approach 1:
The patent divides the bus architecture into separate code bus and data bus, allowing independent operation of code execution and data transfer functions. This segmentation eliminates the congestion problem of shared bus usage while maintaining manageable system complexity through functional separation.
Solution Approach 2:
The patent introduces a DMA controller as an intermediary component that manages data transfers independently from the processor. This mediator enables parallel operations where the processor can execute code while the DMA controller handles data transfers, thereby increasing throughput without requiring complex bus arbitration mechanisms.
2Speed
If a multi-bus architecture is implemented to increase data throughput, then data transfer speed improves, but device complexity increases
Solution Approach 1:
The controller architecture is segmented into distinct functional units with dedicated buses: a code bus for processor operations and a data bus for DMA transfers. This segmentation achieves high data transfer speeds through parallel operations while keeping each bus simple and dedicated to a single function, avoiding the complexity of a fully integrated high-speed bus system.
3Productivity
If the bus operates at high speed continuously to maintain high throughput, then data transfer efficiency improves, but power consumption increases
Solution Approach 1:
The patent implements dynamic power management where the DMA controller and data bus can be placed in low-power states when not actively transferring data. The system transitions between active and standby states based on actual data transfer needs, maintaining high transfer efficiency during operation while significantly reducing power consumption during idle periods compared to continuous high-speed operation.
Data Source
AI summary
Systems and methods that can facilitate an expedient and efficient transfer of data between memory components (e.g., flash memory) and host components (e.g., multimedia cards, secure digital cards, etc.) are presented. A memory controller component can be employed to facilitate transferring between the memory components and host components by utilizing a multi-bus architecture. A controller first bus can be utilized for code that can be executed by a controller processor while a controller second bus can be designated for the transfer of data to the mass storage devices. By architecting the memory controller component with two buses, this innovation can provide a higher data throughput than conventional memory controllers.