Multi-Bus RFFE Register Switching Without Clock Synchronization
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Solution Overview
Problem
Modern RF electronic circuits, particularly those requiring simultaneous support of multiple technologies like 4G and 5G, face challenges in accommodating multiple buses due to non-deterministic clock domains, preventing effective common control of agent devices by MIPI RFFE serial buses.
Innovation Solution
The invention employs flagging signals to denote completed register write operations, using a 'last write wins' policy to ensure synchronization in a clock-free manner, allowing common control of agent devices by multiple buses through decoders, multiplexers, and selection circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple MIPI RFFE serial buses are used to control different RF front-end devices, then the system can support multiple technologies (4G and 5G), but the non-deterministic clock domains prevent effective common control of shared agent devices
Solution Approach 1:
A shared decoder is introduced as an intermediary component between multiple MIPI RFFE serial buses and agent devices. This decoder receives serial data from multiple buses with different clock domains and converts them into a unified parallel bus interface, eliminating clock synchronization issues and enabling reliable common control of shared agent devices while maintaining support for multiple technologies
Solution Approach 2:
The control interface is segmented into separate functional parts: multiple MIPI buses remain independent for their respective technologies, while a shared decoder handles the common control function. This segmentation allows each bus to operate independently with its own clock domain while the shared decoder provides a unified interface to agent devices, resolving the contradiction between multi-technology support and reliable common control
2Adaptability or versatility
If a shared decoder is used for common control, then multiple buses can control agent devices, but clock synchronization issues arise
Solution Approach 1:
The patent replaces the complex mechanical/electrical clock synchronization system with a logical/software-based solution. Instead of synchronizing clocks at the hardware level, the shared decoder uses a state machine that tracks the completion status of write operations from different buses and only updates shared registers when a bus has finished its write sequence, eliminating the need for complex clock synchronization circuitry
3Reliability
If deterministic control is implemented, then clock synchronization issues are avoided, but flexibility in control is reduced
Solution Approach 1:
The shared decoder implements a feedback mechanism where each MIPI bus provides completion status signals back to the decoder's state machine. This feedback allows the system to determine when a bus has finished its write operation and update shared registers accordingly. The feedback mechanism provides deterministic control by ensuring writes are completed before register updates, while maintaining flexibility by allowing any bus to write to shared registers at any time as long as it completes its write sequence
Data Source
AI summary
Circuits and methods enabling common control of an agent device by two or more buses, particularly MIPI RFFE serial buses. In essence, the invention provides flagging signals designating completed register write operations to denote which of two registers are active, such that synchronization is accomplished in a clock-free manner. One embodiment includes at least two decoders, each including a common register and a bus (S/P) decoder coupled to a respective bus and to the common register. The S/P decoder asserts a write-complete signal when a write operation to a corresponding common register is completed. A multiplexer has at least two selectable input bus ports coupled to the common registers within the at least two decoders. A selection circuit selects an input bus port of the multiplexer in response to the assertion of a last write-complete signal from the S/P decoders.