Multi-Capacitance Semiconductor Layout for Stable High-Frequency Impedance
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Solution Overview
Problem
Existing semiconductor devices with multiple capacitance sections face challenges in maintaining unchanged characteristics other than capacitance, particularly experiencing significant impedance changes in high frequency ranges when capacitance is altered.
Innovation Solution
A semiconductor device design featuring multiple capacitance sections with different electrostatic capacities, where the inductance of lead wires is carefully controlled to maintain a ratio of 0.8 to 1.2, ensuring minimal impedance change in high frequency ranges by adjusting the inductance of lead wires through the use of inductance adjusting wires like meander or spiral configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple capacitance sections with different electrostatic capacities are provided in one chip, then versatility for various applications is improved, but impedance change in high frequency range increases
Solution Approach 1:
The patent applies local quality by making each capacitance section have different inductance characteristics tailored to its specific capacitance value. The lead wire inductances are individually adjusted (L1/L2=0.8 to 1.2) so that each capacitance section maintains stable impedance characteristics in its intended frequency range, rather than using uniform lead wire designs for all sections.
Solution Approach 2:
The patent changes the inductance parameter of the lead wires to resolve the contradiction. By adjusting the inductance values of lead wires connected to different capacitance sections and maintaining their ratio within 0.8 to 1.2, the patent ensures that impedance characteristics remain stable across different frequency ranges when switching between capacitance sections, thus enabling versatility without sacrificing reliability.
2Adaptability or versatility
If capacitance value is changed by switching between capacitance sections, then adaptability is improved, but other characteristics such as frequency characteristic of impedance are changed
Solution Approach 1:
Each capacitance section is designed with locally optimized inductance characteristics through customized lead wire inductances. This local quality approach ensures that when switching between different capacitance values, the frequency characteristics remain stable because each section's inductance is specifically tailored to compensate for capacitance changes.
Solution Approach 2:
The patent employs parameter changes by adjusting the inductance values of lead wires to compensate for capacitance variations. By controlling the inductance ratio L1/L2 within 0.8 to 1.2, the patent maintains stable frequency characteristics across different capacitance sections, allowing capacitance value adaptability without compromising frequency characteristic stability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design effectively minimizes impedance changes in high frequency ranges when capacitance is varied, allowing for versatile applications while maintaining consistent impedance characteristics across different frequency ranges.
Implementation Method 1
a first lead wire led out from the first capacitance section to the first external electrode and having an inductance L1; and a second lead wire led out from the second capacitance section to the second external electrode and having an inductance L2
Data Source
AI summary
A semiconductor device that includes a semiconductor substrate; a first capacitance section on the semiconductor substrate, the first capacitance section including a first electrode layer, a first dielectric layer, and a second electrode layer; a second capacitance section on the semiconductor substrate, the second capacitance section including a third electrode layer, a second dielectric layer, and a fourth electrode layer; a first external electrode; a second external electrode; a first lead wire led out from the first capacitance section to the first external electrode and having an inductance L1; and a second lead wire led out from the second capacitance section to the second external electrode and having an inductance L2, wherein an electrostatic capacity C1 of the first capacitance section and an electrostatic capacity C2 of the second capacitance section are different, and L1/L2=0.8 to 1.2.