Multi-Capacitor ADC Sampling for Anti-Aliasing at Lower Power
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Solution Overview
Problem
Existing sampling circuits, such as those in analog-to-digital converters, face challenges with noise sensitivity and aliasing due to high-frequency signals, requiring energy-efficient solutions with low power consumption and high sampling rates.
Innovation Solution
The use of multiple capacitors to sample an analog input signal at distinct times, with circuitry to combine samples and generate a digital output, and the selection of capacitor sets to match anti-aliasing filter responses, allowing for increased effective sampling rates and intrinsic decimation to reduce aliasing noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If an active filter is used to reduce aliasing noise, then aliasing noise is reduced, but additional noise is introduced by the active filter and additional current is required
Solution Approach 1:
The patent replaces active filtering (which requires power and introduces noise) with a passive capacitive sampling approach. Multiple capacitors sample the input signal at different times during the sampling interval, and the charge is combined during conversion. This substitution of active electronic filtering with passive capacitive charge storage and combination eliminates the need for additional current while avoiding the introduction of filter noise.
Solution Approach 2:
The patent performs preliminary sampling actions by using multiple capacitors to capture the input signal at different time points within the sampling interval before the conversion phase. This preliminary multi-point sampling allows the system to inherently reject aliasing components without requiring subsequent active filtering, thereby avoiding additional power consumption and noise introduction.
2Object-affected harmful factors
If the sampling rate is increased to avoid aliasing, then aliasing is reduced, but power consumption increases
Solution Approach 1:
The patent segments the sampling process by dividing the sampling interval into multiple discrete sampling points, each captured by a separate capacitor. Instead of requiring a high sampling rate to capture all signal variations, the system segments the signal capture into multiple lower-rate samples that are then combined during conversion. This segmentation allows aliasing rejection without the power penalty of uniformly high-rate sampling across the entire system.
Solution Approach 2:
The patent employs periodic action by having multiple capacitors sample the input signal at different time points within each sampling interval in a periodic manner. The capacitors are sequentially connected to the input during the sampling phase, creating a periodic sampling pattern that effectively rejects aliasing components while maintaining a lower overall sampling rate requirement, thus reducing power consumption compared to continuous high-rate sampling.
3Measurement precision
If multiple capacitors are used to sample at distinct times, then accuracy and noise sensitivity are improved, but device complexity increases
Solution Approach 1:
The patent merges the samples from multiple capacitors by combining their stored charge during the conversion phase. All capacitors are connected to a common conversion circuitry where their individual samples are summed together. This merging approach allows the system to achieve improved sampling accuracy through multiple time-point sampling while avoiding the complexity of processing and managing separate sample streams, as the charge combination occurs naturally in the analog domain.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the accuracy and reduces noise sensitivity of sampling circuits by effectively capturing high-frequency signals and processing them through anti-aliasing filtering, achieving lower power consumption and improved performance.
Implementation Method 1
a first capacitor samples an analog input signal at a first time during a sampling time interval. A second capacitor samples the analog input signal at a second time during the sampling time interval
Data Source
AI summary
A sampling circuit, such as the sampling circuit of a successive approximation analog-to-digital converter (ADC), provides anti-aliasing filtering of a sampled input signal. The circuit samples the input signal using multiple capacitors, wherein each capacitor samples the input signal at a distinct time during a sampling time interval. The circuit combines the samples stored on different capacitors during a conversion time interval, and generates a digital output signal using the combined samples. In one example, a first bit of the output signal is generated using a sample stored on a first capacitor, and second bit of the output signal is generated using a sample stored on a second capacitor. In another example, the circuitry performs finite or infinite impulse response (FIR or IIR) filtering of the input signal, where a filter characteristic is determined by the relative sizes of the capacitors used for sampling.