Multi-Carrier Electronic Package Bridging to Prevent Warpage
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Solution Overview
Problem
Conventional semiconductor packages face issues with warpage and cracking due to increased area requirements for multiple chips on a single silicon interposer, leading to poor yield and reliability, and thickness increases from additional redistribution layers.
Innovation Solution
The use of multiple carrier structures with bridging elements that electrically connect adjacent structures, allowing for increased functionality without expanding the area of each carrier structure, thereby reducing stress and eliminating the need for additional redistribution layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the area of the chip-mounting side of the silicon interposer is increased to accommodate multiple semiconductor chips, then the functionality of the semiconductor package is improved, but warpage occurs leading to poor contact or cracking of the semiconductor chips or conductive elements
Solution Approach 1:
The patent divides the single large silicon interposer into multiple smaller carrier structures (first carrier structure, second carrier structure, etc.). Each carrier structure has a controlled area that avoids warpage while collectively supporting multiple semiconductor chips. The carrier structures are electrically connected through conductive elements to form a unified system.
2Adaptability or versatility
If the area of the chip-mounting side of the silicon interposer is increased to accommodate multiple semiconductor chips, then the functionality of the semiconductor package is improved, but the silicon interposer is prone to cracking due to stress concentration
Solution Approach 1:
The patent segments the large interposer area into multiple smaller carrier structures, each with dimensions that avoid stress concentration. This segmentation distributes the mechanical stress across multiple smaller units rather than concentrating it in one large structure, preventing cracking while maintaining the ability to support multiple chips.
3Reliability
If the area of the chip-mounting side of the silicon interposer is not increased, then the warpage and cracking problems are avoided, but the number of layers of the redistribution layer needs to be increased which increases the overall thickness
Solution Approach 1:
Instead of increasing the number of redistribution layers in the vertical dimension (which increases thickness), the patent uses horizontal electrical connections between adjacent carrier structures through conductive elements. This lateral connectivity approach achieves the same functional goal without adding vertical layers, thus maintaining thin profile while preserving structural stability.
4Adaptability or versatility
If the number of layers of the redistribution layer is increased to maintain electrical connections without increasing area, then the routing capability is improved, but the process yield decreases
Solution Approach 1:
The patent segments the electrical connection function across multiple carrier structures connected by conductive elements. This approach provides flexible routing capability through the network of connected carriers without requiring complex multi-layer redistribution schemes, thereby maintaining higher process yield.
Data Source
AI summary
An electronic package is provided, in which a plurality of electronic elements are disposed on a plurality of carrier structures, and at least one bridging element is disposed between at least two of the carrier structures to electrically bridge the two carrier structures. Therefore, when there is a need to increase the function of the electronic package, only one electronic element is arranged on a single carrier structure, and there is no need to increase the panel area of the carrier structure, so as to facilitate the control of the panel area of the carrier structure and avoid warpage of the carrier structure due to the oversized panel.