Multi-Channel ADC Interleaved Sampling to Reduce Channel Mismatch

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Solution Overview

Problem

Conventional data acquisition systems require multiple sample/hold blocks or ADCs for multiple channels, which are sensitive to high-frequency noise and lead to increased power consumption, die area, and cost, with potential mismatches between channels.

Innovation Solution

A multi-channel analog to digital converter (ADC) with a first and second sampling-integrating unit in series, coupled with a feedback circuit, that samples and integrates analog signals across multiple channels in an interleaved mode, reducing the need for multiple sample/hold blocks or ADCs and minimizing channel mismatches.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If multiple sample/hold blocks are used for multiple channels, then simultaneous sampling capability is improved, but device complexity and sensitivity to high-frequency noise increase

Engineering Contradiction:
Improvesimultaneous sampling capabilityVSAvoiddevice complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The patent segments the sampling process into multiple sequential stages (first sampling-integrating unit, second sampling-integrating unit, etc.) that operate in series. Each stage processes a portion of the conversion, allowing simultaneous sampling capability while avoiding the complexity of multiple parallel sample/hold blocks. The segmentation of the conversion process into sequential stages resolves the contradiction by achieving parallel sampling throughput through serial processing architecture.

Inventive Principle:
Principle #1Segmentation

2Productivity

If multiple ADCs are employed for each input channel, then conversion capability is improved, but power consumption and die area increase

Engineering Contradiction:
Improveconversion capabilityVSAvoidpower consumption
Core Design Contradiction:
ProductivityVSUse of energy by moving object

Solution Approach 1:

The patent merges multiple conversion functions into a single multi-channel ADC architecture. Instead of employing separate ADCs for each input channel, the invention combines multiple sampling-integrating units and feedback circuits into one integrated converter that handles multiple channels sequentially. This merging approach maintains high conversion capability while significantly reducing power consumption and die area compared to using multiple independent ADCs.

Inventive Principle:
Principle #5Merging (Combining)

3Productivity

If multiple ADCs are used for synchronization, then conversion capability is improved, but channel mismatch and cost increase

Engineering Contradiction:
Improveconversion capabilityVSAvoidchannel mismatch
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent creates a universal multi-channel ADC architecture where a single converter performs the conversion function for multiple input channels. The sampling-integrating units and feedback circuits are designed to handle different channels through a unified process, ensuring consistent conversion characteristics across all channels. This multi-functional design eliminates channel mismatch issues that arise from using multiple different ADCs while maintaining high conversion capability.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS8193959B2Analog to digital converters
Publication Date: 2012.06.05 O2 MICRO INT LTD
  • US8193959B2 patent drawing
  • US8193959B2 patent drawing
  • US8193959B2 patent drawing

AI summary

In one embodiment, an analog to digital converter (ADC) for converting an analog signal to a digital signal includes an input channel for receiving the analog signal, and includes a first and second sampling-integrating units. The first sampling-integrating unit receives the analog signal, samples the analog signal, integrates a superposition of a first feedback signal and a sampled signal of the analog signal, and generates a first output signal. The second sampling-integrating unit receives the first output signal, samples the first output signal, integrates a superposition of a second feedback signal and a sampled signal of the first output signal, and generates a second output signal. The ADC includes a feedback circuit for generating the digital signal according to the second output signal and for providing the first and second feedback signals indicative of the digital signal to the first and second sampling-integrating units respectively.