Multi-channel Cache Memory Address Routing
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Solution Overview
Problem
Processing apparatus face slower memory access speeds due to contention between parallel accesses and inherent limitations in memory storage access speed, necessitating efficient cache memory management to maintain coherency across multiple processing units.
Innovation Solution
A multi-channel cache memory system where each cache channel serves a unique portion of the memory address space, with arbitration circuitry routing memory access requests to the appropriate cache channel based on the memory address, ensuring parallel processing and independent allocation regardless of the processing unit's identity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a shared cache memory unit with integrated crossbar is used to serve multiple processing units, then cache capacity is improved, but access speed deteriorates due to contention between parallel accesses
Solution Approach 1:
The cache memory is divided into multiple independent cache channels, each serving a specific portion of the address space. This segmentation eliminates contention between parallel accesses by providing dedicated access paths, thereby maintaining high access speed while preserving total cache capacity.
Solution Approach 2:
The patent introduces a new dimension of address space partitioning by mapping different portions of the address space to different cache channels. This dimensional organization allows parallel processing units to access different cache channels simultaneously without interference, resolving the speed-capacity tradeoff.
2Speed
If separate caches are allocated to each processing unit to eliminate contention, then access speed is improved, but device complexity increases due to multiple cache structures
Solution Approach 1:
The cache memory structure serves multiple functions: it provides dedicated access paths for different processing units while maintaining a unified address space mapping. The same cache physical memory is accessed through different channels based on address portion, eliminating the need for completely separate cache structures for each processing unit.
Solution Approach 2:
The patent introduces an address routing mechanism that acts as an intermediary between processing units and cache memory. This mediator directs access requests to the appropriate cache channel based on the address portion, providing dedicated access without requiring physically separate cache structures for each processing unit.
3Productivity
If caches are physically separated for different processing units, then access independence is improved, but coherency maintenance becomes more difficult due to lack of isolation
Solution Approach 1:
The patent applies local quality by assigning specific portions of the address space to specific cache channels. This creates natural isolation zones where each cache channel independently manages its designated address space portion, providing both access independence and simplified coherency management through spatial separation of address ranges.
Data Source
AI summary
A cache memory including: a plurality of parallel input ports configured to receive, in parallel, memory access requests wherein each parallel input port is operable to receive a memory access request for any one of a plurality of processing units; and a plurality of cache blocks wherein each cache block is configured to receive memory access requests from a unique one of the plurality of input ports such that there is a one-to-one mapping between the plurality of parallel input ports and the plurality of cache blocks and wherein each of the plurality of cache blocks is configured to serve a unique portion of an address space of the memory.