Multi-Channel Comparator Layout for Low-Kickback SAR ADCs

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Solution Overview

Problem

SAR analog-to-digital converters face issues with increased input capacitance and kickback noise due to the use of strongARM latch comparators, which affect the input signal and reduce conversion accuracy.

Innovation Solution

A comparator design with alternately operating channels that share a single input circuit, using clocking transistor circuits to alternately activate sense amplifying circuits, reducing input capacitance and minimizing kickback noise.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If a strongARM latch comparator is used, then conversion speed is improved, but kickback noise increases and input capacitance increases

Engineering Contradiction:

Improveconversion speedVSAvoidkickback noise

Core Design Contradiction:

SpeedVSObject-generated harmful factors

Solution Approach 1:

The comparator is divided into multiple channels (first channel with first sense amplifying circuit, second channel with second sense amplifying circuit) that operate alternately. Each channel has its own sense amplifying circuit but shares a common input circuit, allowing the comparator to maintain fast conversion speed while reducing kickback noise through alternating operation modes

Inventive Principle:

Principle #1Segmentation

2Measurement precision

If multiple sense amplifying circuits are used, then comparison accuracy is improved, but input capacitance increases

Engineering Contradiction:

Improvecomparison accuracyVSAvoidinput capacitance

Core Design Contradiction:

Measurement precisionVSQuantity of substance

Solution Approach 1:

The multiple sense amplifying circuits operate in periodic alternating fashion controlled by clock signals. The first sense amplifying circuit operates during first time intervals while the second operates during second time intervals, allowing multiple high-precision comparison circuits to function without simultaneously loading the input, thus maintaining low input capacitance

Inventive Principle:

Principle #19Periodic action

3Loss of energy

If alternately operating channels are used, then power consumption is reduced, but device complexity increases

Engineering Contradiction:

Improvepower consumptionVSAvoiddevice complexity

Core Design Contradiction:

Loss of energyVSDevice complexity

Solution Approach 1:

The input circuit is merged and shared between multiple channels, while each channel has its own sense amplifying circuit. The clocking transistor circuits are configured to alternately activate different channels, reducing overall power consumption while the shared input circuit minimizes the increase in device complexity

Inventive Principle:

Principle #5Merging (Combining)

Data Source

PatentUS20250317132A1Comparator including plurality of channel circuits and analog-to-digital converter including the same

Publication Date: 2025.10.09 SAMSUNG ELECTRONICS CO LTD

AI summary

A comparator includes an input circuit that receives a first input signal and a second input signal, a first sense amplifying circuit that generates a first output signal and a second output signal by amplifying a potential difference between the first input signal and the second input signal, a first clocking transistor circuit that connects the input circuit to the first sense amplifying circuit based on a first clock signal, a second sense amplifying circuit that generates a third output signal and a fourth output signal by amplifying the potential difference between the first input signal and the second input signal, and a second clocking transistor circuit that connects the input circuit to the second sense amplifying circuit based on a second clock signal.