Multi-Channel Digital Step Attenuator Architecture for Glitch Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing digital step attenuators (DSAs) face challenges with transient glitches due to asymmetrical switching times of component elements, and require finer resolution and larger range to resolution ratios, leading to manufacturability issues, especially in high-resolution applications.
Innovation Solution
A multi-channel DSA architecture with N channels of B selectable RF attenuator cells, each having two states, improves transient glitch behavior and allows for more uniform MSB to LSB ratios and fine resolution step sizes by mitigating switching transients across parallel channels, using attenuator networks like Bridged-Tee, Pi, or L-pad types, and varying design parameters such as the number of cells, channels, and characteristic impedances.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If binary-weighted attenuator cells are used to provide selectable attenuation levels, then the DSA can achieve fine resolution step sizes, but transient glitches occur due to asymmetrical switching times of the switching elements
Solution Approach 1:
The patent divides the single-channel DSA into multiple parallel channels, each containing a subset of the attenuator cells. By segmenting the switching events across multiple channels, the patent reduces the cumulative transient glitch effect at any given time, while maintaining the fine resolution capability through the combined attenuation of all channels.
Solution Approach 2:
The patent changes the architectural parameter from a single-channel to a multi-channel configuration. This parameter change fundamentally alters how attenuation is achieved, distributing the switching transients across multiple independent channels and reducing the overall glitch impact while preserving resolution through the combined effect of all channels.
2Measurement precision
If the number of attenuator cells is increased to achieve finer resolution, then the step size decreases, but the manufacturability becomes more challenging due to extreme MSB to LSB attenuation ratios
Solution Approach 1:
The patent segments the total attenuation range across multiple parallel channels, where each channel handles a portion of the total attenuation. This segmentation reduces the MSB to LSB attenuation ratio within each individual channel, making the resistor values more uniform and easier to manufacture with standard precision resistors.
Solution Approach 2:
The patent changes the distribution of attenuation values across channels, transforming the extreme MSB to LSB ratio problem into a more manageable set of ratios within each channel. This parameter change enables the use of standard resistor precision (e.g., 1% or 5%) while achieving fine overall resolution.
3Measurement precision
If high-resolution DSAs with small attenuation ranges are designed, then the LSB attenuation value becomes extremely small, but this increases the complexity of resistor precision requirements
Solution Approach 1:
The patent segments the high-resolution attenuation requirement across multiple parallel channels, distributing the small LSB attenuation value requirement across several channels rather than requiring extreme precision in a single channel. Each channel can use standard precision resistors while the combined effect achieves the required fine resolution.
Solution Approach 2:
The patent merges the output of multiple parallel channels to achieve the final high-resolution attenuation. By combining the attenuation effects of multiple channels with standard precision resistors, the system achieves fine LSB resolution without requiring extremely precise individual resistors in each channel.
4Reliability
If more attenuator channels are added to reduce transient glitches, then the transition levels are reduced by 1/N, but the device complexity increases
Solution Approach 1:
The patent segments the attenuator cells across multiple parallel channels, which reduces transient glitches by distributing switching events. The segmentation approach achieves glitch reduction while managing complexity through systematic organization of the parallel channels and their control logic.
Data Source
AI summary
A multi-channel digital step attenuator (DSA) architecture. One embodiment includes an array comprising N channels of B selectable attenuator cells series-connected. The overall impedance of a multi-channel DSA is a function of the parallel impedances of the N channels, and transition levels are reduced by 1/N since the transient effect of switching any one attenuator cell in or out of circuit in one channel is mitigated by all other in-circuit attenuator cells in the parallel channels. The multi-channel DSA architecture enables a great design flexibility, and allows a designer to vary one or more of at least the following design parameters: the number of attenuator cells B per channel; the number N of channels per DSA; the bit weighting of each attenuator cell per channel; the maximum attenuation per channel; and the characteristic impedance Zon of each channel.