Multi-Channel ECC Rotation to Preserve Memory Bandwidth
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Solution Overview
Problem
Standard DRAM memory with ECC logic is not suitable for systems requiring high storage capacity and bandwidth due to cost, design limitations, and availability issues, leading to reduced bandwidth when implementing error correction methods.
Innovation Solution
A method for writing and reading data that simultaneously writes or reads error correction codes to a different channel in a multi-channel memory module, maintaining bandwidth by incrementing the channel index and alternating the start value for each operation, allowing parallel processing of data and error correction codes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ECC logic is implemented in memory controller with dual write/read access, then data integrity is improved, but channel bandwidth is reduced by half
Solution Approach 1:
The patent transitions from single-channel sequential access to multi-channel parallel access, adding a spatial dimension to the data storage architecture. By distributing data and ECC codes across multiple channels, the system achieves both data integrity and maintained bandwidth through parallel operations.
Solution Approach 2:
The patent divides the memory system into multiple independent channels, each handling specific data and ECC code pairs. This segmentation allows parallel processing of multiple data-ECC pairs simultaneously, preventing bandwidth reduction while maintaining data integrity through distributed error correction.
2Reliability
If standard DRAM memory with ECC logic is used, then error correction capability is improved, but cost and design complexity increase
Solution Approach 1:
The patent extracts the ECC logic from the memory chips themselves and relocates it to the memory controller. This separation allows the use of simpler, more cost-effective memory chips while maintaining error correction capability through controller-based ECC processing across multiple channels.
Data Source
AI summary
A write or read method for use in a computer having multiple channels of memory includes writing or reading data to or from one channel in the memory, and simultaneously in parallel writing or reading an error correction code corresponding to the data to or from a different channel in the memory.