Multi-channel Encryption Pipeline Architecture
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Solution Overview
Problem
Existing high-speed hardware implementations of cryptographic algorithms face limitations such as inflexibility, restricted input/output timing, and limited capability to handle data from multiple channels, making them unsuitable for modern high-rate transmission systems.
Innovation Solution
A scalable and efficient cryptographic architecture is implemented using deeply-pipelined algorithms and circuitries, allowing for zero-latency switching between cryptographic channels and partial consolidation of hash information, enabling processing of data from multiple channels with flexible throughput and parallelism.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If pipelining and unrolling techniques are used to speed up cryptographic processing, then processing speed is improved, but interface timing becomes very restrictive and the hardware core becomes difficult to use
Solution Approach 1:
The cryptographic processing system is divided into multiple independent hardware cores, each capable of handling specific encryption or authentication operations. This segmentation allows each core to operate with its own timing requirements while maintaining overall system throughput through parallel processing of multiple data channels.
2Speed
If fixed-time interface requirements are imposed on hardware cores, then processing speed is improved, but the system becomes slower and larger when using discrete hardware cores
Solution Approach 1:
Multiple cryptographic hardware cores are merged into a unified architecture that shares common resources such as memory interfaces and control logic. This merging enables the system to achieve high throughput by processing multiple data channels simultaneously while reducing overall system size and improving resource utilization compared to discrete core implementations.
3Device complexity
If hardware implementations are designed for single-channel processing, then device complexity is reduced, but capability to handle multichannel data is limited
Solution Approach 1:
The cryptographic hardware cores are designed with universal interfaces and control mechanisms that enable them to handle multiple data channels with different protocols and encryption requirements. The architecture supports dynamic configuration and can adapt to various cryptographic algorithms and data formats without requiring separate dedicated hardware for each channel.
Data Source
AI summary
A scalable and efficient cryptographic architecture is provided for processing data using deeply-pipelined algorithms and circuitries. The architecture can be implemented as circuitry in a fixed logic device, or can be configured into a programmable integrated circuit device. The same top-level design may be used for different choices of data channels, processing depth, parallelism level, and/or system throughput. An encryption pipeline processing block performs rounds of processing upon a block of said data using an encryption process and receives a respective round encryption key for each round of processing. An encryption key pipeline block provides the respective round encryption key for each round of processing by selecting, for each round of processing, the respective round encryption key from at least a first round encryption key corresponding to a first channel and a second round encryption key corresponding to a second channel.