Multi-channel Ferroelectric Memory Structure for High Speed
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Solution Overview
Problem
Ferroelectric memory cells have a relatively low ON/OFF current ratio, which affects their performance by causing slow read and write speeds and increased power consumption, limiting their applications in high-speed and ultra-low power applications.
Innovation Solution
A multi-channel ferroelectric memory structure is developed, featuring a plurality of individual channel structures and insulator structures alternately stacked, which increases the ON current and decreases the OFF current, thereby enhancing the ON/OFF current ratio.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a conventional single-channel ferroelectric memory structure is used, then the device complexity is low, but the ON/OFF current ratio is low resulting in slow read/write speeds and high power consumption
Solution Approach 1:
The channel structure is segmented into multiple individual channels (first channel structure, second channel structure, third channel structure, fourth channel structure) that are vertically stacked and electrically isolated from each other by insulator structures. This segmentation allows each channel to contribute independently to the total ON current while maintaining separate control, thereby increasing the overall ON/OFF current ratio and improving read/write speeds without requiring a complete redesign of the memory cell architecture.
Solution Approach 2:
The patent transitions from a planar single-channel structure to a vertically stacked multi-channel structure by adding the vertical dimension. Multiple channel structures are arranged in the vertical direction with insulator structures between them, effectively utilizing three-dimensional space. This dimensional change increases the effective channel width and ON current capability while maintaining a compact footprint, thus improving productivity without proportionally increasing device complexity.
2Use of energy by moving object
If a conventional single-channel ferroelectric memory structure is used, then the manufacturing process is simple, but the power consumption is high due to low ON/OFF current ratio
Solution Approach 1:
The channel structure is segmented into multiple individual channels (first channel structure, second channel structure, third channel structure, fourth channel structure) that are vertically stacked and electrically isolated from each other by insulator structures. This segmentation allows each channel to contribute independently to the total ON current while maintaining separate control, thereby increasing the overall ON/OFF current ratio and improving read/write speeds without requiring a complete redesign of the memory cell architecture.
Solution Approach 2:
The patent transitions from a planar single-channel structure to a vertically stacked multi-channel structure by adding the vertical dimension. Multiple channel structures are arranged in the vertical direction with insulator structures between them, effectively utilizing three-dimensional space. This dimensional change increases the effective channel width and ON current capability while maintaining a compact footprint, thus improving productivity without proportionally increasing device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The multi-channel ferroelectric memory structure improves the ON/OFF current ratio, enabling faster data processing and reduced power consumption, thus expanding its applications to include high-speed and ultra-low power data applications.
Implementation Method 1
Some promising candidates for next generation memory technology utilize ferroelectricity to store data, such as ferroelectric field-effect transistor (FeFET) memory
Data Source
AI summary
Various embodiments of the present disclosure are directed towards an integrated chip (IC) comprising a first electrode structure disposed in a substrate. A first ferroelectric structure is disposed on a first side of the first electrode structure. A channel structure is disposed on a first side of the first ferroelectric structure. The channel structure includes a plurality of individual channel structures and a plurality of insulator structures. The plurality of individual channel structures and the plurality of insulator structures are alternately stacked. A pair of source/drain (S/D) structures are disposed on the first side of the first ferroelectric structure. The pair of S/D structures extend vertically through the channel structure, and the first electrode structure is disposed laterally between the S/D structures of the pair of S/D structures.