Multi-Channel Gate Structure for Lower Subthreshold Leakage
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Solution Overview
Problem
Semiconductor devices face challenges in reducing sub-threshold leakage current and enhancing operating threshold voltage distribution due to the miniaturization of transistors with three-dimensional channel structures.
Innovation Solution
A semiconductor device with vertically spaced channel layers, including a plurality of channel layers and a gate structure that adjusts work function to prevent parasitic threshold voltage formation, thereby reducing sub-threshold leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transistors with three-dimensional channel structures are miniaturized to increase integration, then device density is improved, but sub-threshold leakage current increases
Solution Approach 1:
The channel is segmented into multiple separate channel layers (first channel layer, second channel layer, third channel layer) positioned at different heights. This segmentation allows each layer to contribute to the total channel conductivity while maintaining better control over leakage paths, thereby reducing sub-threshold leakage current while preserving high device density through vertical integration.
Solution Approach 2:
The invention transitions from a planar two-dimensional channel structure to a three-dimensional multi-layer channel structure. By distributing channel layers vertically at different heights (first, second, and third channel layers), the device achieves higher integration density without proportionally increasing leakage current, as the vertical separation provides additional control over carrier transport and leakage paths.
2Productivity
If transistors with three-dimensional channel structures are miniaturized to increase integration, then device density is improved, but operating threshold voltage distribution deteriorates
Solution Approach 1:
Different channel layers are assigned different local characteristics: the first channel layer has a first threshold voltage, the second channel layer has a second threshold voltage, and the third channel layer has a third threshold voltage. This local differentiation allows precise control over the overall threshold voltage distribution, improving manufacturing precision while maintaining high device density through vertical stacking.
Solution Approach 2:
The channel is divided into multiple segments (channel layers) that can be independently controlled. By segmenting the channel into distinct layers with potentially different dopant concentrations and materials, the invention achieves better control over threshold voltage distribution, reducing variability and improving manufacturing precision despite miniaturization.
3Object-generated harmful factors
If vertically spaced channel layers are used to reduce sub-threshold leakage current, then leakage current is reduced, but device complexity increases
Solution Approach 1:
Multiple channel layers are nested within the same transistor structure at different vertical positions. The first, second, and third channel layers are all contained within the device footprint, with gate structures surrounding each layer. This nested arrangement reduces leakage current through vertical separation while minimizing the increase in overall device complexity by utilizing the vertical dimension efficiently.
Solution Approach 2:
The invention resolves the complexity issue by utilizing the vertical dimension to separate channel layers. Instead of increasing lateral complexity to reduce leakage, the solution moves to the vertical dimension, where channel layers are spaced apart in the height direction. This approach reduces leakage current while keeping the planar device footprint compact and manageable.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Significantly reduces sub-threshold leakage current and enhances operating threshold voltage distribution, improving the electrical characteristics and performance of the semiconductor device.
Implementation Method 1
The first gate electrode includes a first lower electrode portion between the first active fin and the first lower channel layer, a first intermediate electrode portion between the first lower channel layer and the first intermediate channel layer, and a first upper electrode portion between the first intermediate channel layer and the first upper channel layer
Implementation Method 2
sub-threshold leakage current may be significantly reduced or prevented in a transistor including a plurality of vertically spaced channel layers
Data Source
AI summary
A semiconductor device includes a substrate, an active fin on the substrate, and a transistor on the active fin. The transistor includes a lower channel layer, an intermediate channel layer, and an upper channel layer sequentially stacked, and a gate structure traversing the active fin, respectively surrounding the channel layers, and including a gate dielectric and a gate electrode. The gate electrode includes a lower electrode portion between the active fin and the lower channel layer, an intermediate electrode portion between the lower channel layer and the intermediate channel layer, and an upper electrode portion between the intermediate channel layer and the upper channel layer. The gate electrode includes a work function adjusting metal element, and a content of the work function adjusting metal element in the lower electrode portion is different from that in each of the intermediate electrode portion and the upper electrode portion.