Multi-Channel GaN HEMT Drift Region for Low On-Resistance
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Solution Overview
Problem
High-electron-mobility transistors (HEMTs) face challenges in achieving low on-resistance and high voltage handling capabilities due to limitations in the drift region resistance, which affects their performance in power management and RF applications.
Innovation Solution
The implementation of a multi-channel structure with stacked channel layers in the drift region, coupled to a single channel layer under the gate structure, reduces overall resistance through parallel conduction paths and enhances voltage handling by using GaN/AlGaN materials, along with buried via structures and isolation regions to connect multiple layers to a drain ohmic contact.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single channel layer is used under the gate structure, then the device structure is simple, but the on-resistance is high and voltage handling capability is limited
Solution Approach 1:
The patent transitions from a single 2D channel layer to a three-dimensional stacked channel structure with multiple channel layers arranged vertically in the drift region. This dimensional change enables parallel conduction paths while maintaining a compact footprint, thereby reducing on-resistance and enhancing voltage handling capability without proportionally increasing device area.
Solution Approach 2:
The channel region is segmented into multiple discrete channel layers stacked vertically, with each layer providing an independent conduction path. These segmented channels are electrically connected through buried via structures, creating parallel current paths that reduce overall on-resistance while distributing the voltage handling stress across multiple layers.
2Reliability
If multiple channel layers are stacked in the drift region, then on-resistance is reduced through parallel conduction paths, but the device structure becomes more complex
Solution Approach 1:
Multiple channel layers are merged into a single integrated stacked structure that functions as one unified conduction system. The channels are electrically connected through buried via structures and isolation regions, combining their conduction capabilities to achieve lower on-resistance while presenting a compact, integrated device architecture.
Solution Approach 2:
The channel layers are nested vertically within the drift region, with each channel layer containing conduction paths that are electrically connected to underlying layers through buried via structures. This nested arrangement allows multiple conduction paths to be packed into a compact vertical space, reducing on-resistance without proportionally increasing device footprint.
3Reliability
If GaN/AlGaN materials are used for high voltage handling, then voltage handling capability is improved, but manufacturing complexity increases
Solution Approach 1:
The patent utilizes parameter changes in material composition, specifically varying the aluminum content in AlGaN barrier layers across different channel layers to optimize both voltage handling capability and conduction properties. This parameter adjustment enables tailored performance characteristics while maintaining compatibility with standard GaN HEMT fabrication processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration achieves ultra-low on-resistance with large voltage handling capabilities, improving the efficiency and performance of HEMTs in power management and RF applications.
Implementation Method 1
multiple channel layers in the drift region coupled to the single channel layer under the gate structure
Data Source
AI summary
The present disclosure relates to semiconductor structures and, more particularly, to multi-channel transistors and methods of manufacture. The structure includes: a gate structure; a single channel layer in a channel region under the gate structure; a drift region adjacent to the gate structure; and multiple channel layers in the drift region coupled to the single channel layer under the gate structure.