Multi-Channel Memory Channel Allocation for Bandwidth Bottlenecks
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Solution Overview
Problem
Multi-channel memory systems experience bottlenecks when frequent access requests are made to non-consecutive memory addresses, leading to inefficient channel utilization and reduced bandwidth.
Innovation Solution
An operating method for multi-channel memory systems that allocates channels based on additional bits of the memory addresses, allowing for more distributed access across multiple channels, thereby preventing bottlenecks by using a channel interleaving module to allocate channels based on n+1 or more bits of the address, ensuring efficient access across all channels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If channel interleaving method is used to increase bandwidth, then memory access bandwidth is improved, but bottleneck phenomenon occurs when accesses repeatedly occur through one or some channels
Solution Approach 1:
The patent applies dynamics by making the channel allocation strategy adaptable to different access patterns. The system dynamically switches between conventional channel allocation (for sequential access) and additional-bit-based channel allocation (for non-consecutive access), allowing the channel interleaving mechanism to respond to varying access requirements and prevent bottlenecks under different workload conditions
Solution Approach 2:
The patent changes the parameter used for channel allocation from conventional address bits to additional bits of the address. This parameter change enables more uniform distribution of access requests across multiple channels, particularly for non-consecutive memory addresses, thereby balancing channel utilization and preventing bottleneck phenomena while maintaining high bandwidth
2Device complexity
If conventional channel allocation is used, then simple address mapping is maintained, but channel bottlenecks occur with non-consecutive memory addresses
Solution Approach 1:
The patent introduces an intermediary mechanism (additional bit extraction and channel allocation logic) between the address and the channel selection. This intermediary layer processes the address to extract additional bits and uses them to determine channel allocation, thereby improving channel access efficiency for non-consecutive addresses while adding only moderate complexity through a structured intermediate processing step
Data Source
AI summary
Provided is a system including a multi channel memory and an operating method for the same. The multi channel memory may include a respective set of memories, wherein each set may include one or more memories. The operating method includes receiving access requests including system addresses for a multi channel memory having 2n channels, where n is a natural number greater than 0, allocating a first channel of the 2n channels based on n+1 or more bits of a first address of the system addresses, and performing an access of a respective set of memory devices through the allocated first channel.