Multi-Channel Memory Device with Differentiated Bandwidths for SoC Integration
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Solution Overview
Problem
The increasing complexity of System on Chip (SoC) applications requires a memory device that can efficiently communicate with multiple processing units through varying channels, leading to a need for a memory solution that supports multiple channels with different bandwidths and data exchange speeds, while minimizing device size and cost.
Innovation Solution
A memory device with distinct memory cell areas assigned to different channels, each with its own peripheral circuit and input/output pins, allowing for independent data exchange with SoC processing units through multiple channels, enabling flexible bandwidth and capacity allocation based on SoC requests.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple memory devices are connected for multiple processing units, then communication capability is improved, but device size and cost increase
Solution Approach 1:
The patent combines multiple memory devices into a single integrated memory device that includes multiple memory cell areas (first memory cell area and second memory cell area). This single memory device can serve multiple processing units simultaneously through different channels, thereby improving communication capability while reducing the overall device size and cost compared to using separate memory devices for each processing unit.
Solution Approach 2:
The single memory device is designed with multi-functional capability to serve multiple processing units (first processing unit and second processing unit) through different channels. The memory device can independently access different memory cell areas through different channels, providing universal memory service to multiple processing units without requiring separate dedicated memory devices for each unit.
2Adaptability or versatility
If multiple memory devices are connected for multiple processing units, then communication capability is improved, but cost increases
Solution Approach 1:
The patent merges the functionality of multiple memory devices into a single integrated memory device with multiple memory cell areas and multiple channels. This consolidation reduces the total component count, simplifies the manufacturing process, and lowers overall system cost while maintaining the ability to support multiple processing units with different communication requirements.
Solution Approach 2:
The memory device provides universal access to multiple processing units through a single device architecture, eliminating the need to manufacture and assemble multiple separate memory devices. This multi-functional design reduces manufacturing complexity and cost while enabling flexible communication with different processing units through different channels.
3Productivity
If different bandwidths are allocated to different channels, then communication efficiency is improved, but device complexity increases
Solution Approach 1:
The patent implements local quality by allocating different bandwidths to different channels based on their specific requirements. The first channel can be configured with a first bandwidth for the first processing unit, while the second channel can be configured with a second bandwidth for the second processing unit. This allows each channel to be optimized for its specific communication needs, improving overall communication efficiency while managing device complexity through targeted differentiation rather than uniform design.
Data Source
AI summary
An electronic device includes a memory and a system on chip (SoC). The memory device includes a first memory cell area assigned to a first channel and a second memory cell area assigned to a second channel. The SoC includes a first processing unit and a second processing unit. The first processing unit is configured to transmit a first command for accessing the first memory cell area to the memory device through the first channel. The second processing unit is configured to transmit a second command for accessing the second memory cell area to the memory device through the second channel. The memory device is configured such that a bandwidth of the first channel and a bandwidth of the second channel are different from each other.