Multi-channel Multi-port Memory Dynamic Bank Assignment
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Solution Overview
Problem
Current multi-channel DDR memory systems face limitations in load balancing and memory bank conflicts due to static assignment of memory channels, leading to inefficient access and throughput.
Innovation Solution
A multi-channel multi-port memory architecture that allows access to memory banks from multiple ports and channels, supporting dynamic allocation schemes such as fully shared, even, uneven, and interleaved storage to achieve balanced load and improved bandwidth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If memory channels are statically assigned to memory bank subsets, then each memory controller can access its assigned banks, but memory bank conflicts occur and load balancing becomes difficult
Solution Approach 1:
The patent implements dynamic channel-bank assignment where memory channels can be reassigned to different memory bank subsets based on access patterns. The memory controller dynamically determines which channels access which banks, allowing the system to adapt to varying workload demands and avoid conflicts by redistributing access loads in real-time
Solution Approach 2:
The system changes the assignment parameter (which channel accesses which bank) dynamically based on usage patterns. When certain memory banks are accessed more frequently, the system reconfigures channel assignments to balance the load, transforming the static parameter into a dynamic one that optimizes throughput
2Device complexity
If memory channels are statically assigned to memory bank subsets, then channel structure is simple, but load balancing across memory controllers becomes difficult
Solution Approach 1:
The patent introduces dynamic reconfiguration capability to the channel structure without fundamentally changing its basic architecture. The memory controller can dynamically assign channels to different bank subsets based on load conditions, providing adaptability while maintaining the underlying simple channel structure
Solution Approach 2:
Memory channels are designed to be universal and can be assigned to serve different memory bank subsets depending on the access pattern. Rather than dedicating specific channels to specific banks, each channel can function with multiple bank subsets, enabling flexible load balancing while using the same channel infrastructure
3Device complexity
If each memory channel acts as an independent memory device, then channel organization is simplified, but memory bank conflicts occur when a channel is used repeatedly
Solution Approach 1:
The system dynamically reassigns memory channels to different memory bank subsets based on access patterns. When a particular channel is repeatedly used and conflicts occur, the system can redirect that channel to access a different bank subset, eliminating conflicts and reducing access time while maintaining the independent channel organization
Solution Approach 2:
The memory controller acts as an intermediary that manages the assignment between channels and memory bank subsets. It monitors access patterns and mediates channel assignments to prevent conflicts, allowing channels to serve multiple subsets rather than being rigidly bound to one, thus reducing access time without complicating channel organization
Data Source
AI summary
A multi-channel multi-port memory is disclosed. In a particular embodiment, the multi-channel memory includes a plurality of channels responsive to a plurality of memory controllers. The multi-channel memory may also include a first multi-port multi-bank structure accessible to a first set of the plurality of channels and a second multi-port multi-bank structure accessible to a second set of the plurality of channels.