Multi-Channel Memory Controller for Parallel Data Transmission

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Solution Overview

Problem

Existing data transmission systems face inefficiencies when handling large data transfers or complex data transmission requirements, particularly when multiple memories are involved, as they require extensive link lists and repetitive handshaking processes, leading to reduced transmission efficiency.

Innovation Solution

A data transmission system utilizing two channel control modules that communicate and cooperate to perform union tasks, allowing for independent data transmission between multiple memories, simplifying the process by using switch signals and flag registers to manage data transfer between different memory blocks, and enabling different transmission schemes such as scatter, gather, and link list operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If a single channel control module is used to perform scatter or gather operations, then the module can independently transmit a single memory block of data, but the system requires extensive link lists and repetitive handshaking processes when handling large data transfers or complex transmission requirements, leading to reduced transmission efficiency

Engineering Contradiction:
Improvedata transmission efficiencyVSAvoidlink list complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent divides the channel control functionality into multiple independent channel control modules (first channel control module and second channel control module). Each module can independently perform scatter or gather operations on different memory blocks, eliminating the need for extensive link lists to manage sequential operations. The segmentation allows parallel processing of data transmission tasks across multiple memories.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent combines multiple channel control modules under a unified memory controller that shares common memory interfaces. This merging allows the modules to cooperate on union tasks involving multiple memories without requiring repetitive handshaking processes, as they can simultaneously access different memories through the shared interface.

Inventive Principle:
Principle #5Merging (Combining)

2Productivity

If the data transmission involves multiple different memories, then the system can perform data transfer between multiple memory blocks, but repetitive handshaking processes with different memories are required, thereby lowering the efficiency of data transmission

Engineering Contradiction:
Improvedata transmission efficiencyVSAvoidhandshaking time
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent establishes preliminary connections between channel control modules and multiple memories through shared interfaces. The memory controller is pre-configured with the ability to manage multiple memory blocks simultaneously, so that when data transmission tasks are assigned, the handshaking processes can be initiated in parallel rather than sequentially, reducing the time loss associated with repetitive handshaking.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent enables continuous data transmission operations by allowing multiple channel control modules to work concurrently on different memory blocks. While one module is transmitting data between memories, another module can simultaneously perform handshaking operations, ensuring that the useful action of data transmission continues without interruption or idle waiting time.

Inventive Principle:
Principle #20Continuity of useful action

Data Source

PatentUS11397581B2Data transmission system capable of perform union task with a plurality of channel control modules
Publication Date: 2022.07.26 REALTEK SEMICON CORP
  • US11397581B2 patent drawing
  • US11397581B2 patent drawing
  • US11397581B2 patent drawing

AI summary

A data transmission system includes a first memory, a second memory, a third memory; and a memory controller. The memory controller includes a first channel control module and a second channel control module. The first channel control module is coupled to the first memory and the second memory. The first channel control module transmits a first set of data between the first memory and the second memory, and transmits a switch signal after the first set of data is transmitted. The second channel control module is coupled to the first channel control module, the first memory, and the third memory. The second channel control module transmits a second set of data between the first memory and the third memory after receiving the switch signal.