Multi-channel Memory with Wide IO for High Random Transaction Rates
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Solution Overview
Problem
Conventional quad data rate (QDR) static random access memory (SRAM) devices do not provide the desired random transaction rate (RTR) for many applications, and embedding SRAM into integrated circuits (ICs) to increase RTR can result in inadequate storage, reduced yield, and increased fabrication complexity and cost.
Innovation Solution
The development of integrated circuit memory devices with multiple banks and channels, utilizing a crossbar type arrangement and a wide input/output interface to enable high random transaction rates, where multiple channels can access any memory bank, and incorporating a write cache and error correction mechanisms to optimize data access and storage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional QDR SRAM supports two addresses and data word transfers per interface cycle (two channels), then the device can access two banks in the array, but the random transaction rate does not meet the desired performance for many applications
Solution Approach 1:
The memory device is divided into multiple independently accessible banks (at least two banks), with each bank capable of being accessed by multiple channels. The interface is segmented into multiple channels (at least two channels), where each channel can independently access different banks simultaneously, thereby increasing the overall random transaction rate without proportionally increasing interface complexity
Solution Approach 2:
The interface channels are designed with multi-functionality, where each channel can access any bank in the memory array rather than being dedicated to a specific bank. This universal access capability allows flexible data transfer operations and enables the system to achieve higher random transaction rates by utilizing multiple channels simultaneously for different memory operations
2Productivity
If SRAM memory is embedded into an IC to increase RTR, then the random transaction rate improves, but storage capacity becomes inadequate, yield is reduced, and fabrication complexity and cost increase
Solution Approach 1:
The memory system is segmented into multiple banks that can be independently manufactured and tested. This segmentation allows for modular fabrication processes where each bank can be produced and validated separately, reducing overall fabrication complexity and improving yield while maintaining high random transaction rates through parallel access to multiple banks
Solution Approach 2:
The patent changes the architectural parameters of the memory device by implementing multiple banks and multiple channels with specific access patterns. This parameter change enables high RTR performance without requiring embedding SRAM into the IC, as the multi-channel multi-bank architecture achieves the desired transaction rate through parallelism rather than through integration into the host IC
Data Source
AI summary
An integrated circuit (IC) can include M memory banks, where M is greater than 2, and each memory bank is separately accessible according to a received address value; N channels, where N is greater than 2, and each channel includes its own a data connections, address connections, and control input connections for executing a read or write access to one of the memory banks in synchronism with a clock signal; and a controller subsystem configured to control accesses between the channels and the memory banks, including up to an access on every channel on consecutive cycles of the clock signal.