Multi-Channel Digital Signal Processing via Derived Clock Synchronization
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Solution Overview
Problem
Existing digital transmission systems fail to maximize overall transmission capacity, introduce latency, and require complex information exchange due to inefficiencies in managing multiple channels with varying capacities and protocols, leading to high implementation costs and latency variability.
Innovation Solution
A method that distributes digital data streams across multiple channels by using derived clock signals, status counters, and synchronization signals to ensure maximum capacity utilization without requiring knowledge of the data or protocol, minimizing latency and information exchange between transmitter and receiver.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If reserve channels are kept inactive to ensure transmission reliability, then system reliability is improved, but overall transmission capacity is reduced
Solution Approach 1:
The patent implements dynamic channel management where channels transition between active and reserve states based on real-time quality metrics. The system continuously monitors transmission quality and dynamically adjusts which channels are active versus reserve, allowing optimal capacity utilization while maintaining reliability. This resolves the contradiction by making the reserve channel configuration dynamic rather than static, enabling the system to use more channels when conditions permit while preserving reliability when needed.
2Reliability
If channels are switched off and back on to handle quality variations, then transmission quality is maintained, but transmission latency increases
Solution Approach 1:
The patent pre-establishes multiple channels in an active state with synchronization already configured, rather than switching channels on-demand when quality degrades. By having channels ready in advance with pre-configured synchronization parameters, the system can switch between active channels immediately when quality issues arise, avoiding the time-consuming synchronization restoration process. This preliminary preparation resolves the latency penalty associated with channel switching.
3Productivity
If complex table management is used to optimize channel capacity distribution, then capacity utilization is improved, but device complexity and implementation cost increase
Solution Approach 1:
The patent changes the approach from complex table-based capacity distribution to a simpler parameter-based system. Instead of managing detailed capacity allocation tables, the system uses key parameters such as channel quality metrics, nominal capacities, and dynamic weights to determine channel activation and data distribution. This parameter-driven approach achieves effective capacity utilization while dramatically reducing the complexity of channel management logic and implementation requirements.
4Productivity
If extensive information exchange is performed between transmitter and receiver for channel management, then channel optimization is improved, but information overhead and processing complexity increase
Solution Approach 1:
The patent extracts and separates the essential channel management information from complex protocols, focusing only on the critical parameters needed for optimization. By taking out only the necessary elements (channel quality metrics, capacity information, and activation status) and eliminating redundant information exchange, the system achieves effective channel optimization while minimizing information overhead and simplifying the communication burden between transmitter and receiver.
Data Source
Figure 1~2
AI summary
Method for processing digital signals for transmission/reception from a transmitter (TX) to a receiver (RX) via a transmission management module (GTX) and a reception management module (GRX), on/by a plurality (N) of channels (Ci) with a respective capacity (ci), of a data stream (FTX) comprising, in a time unit (T), an assigned quantity of basic units (Uj) of digital signals not greater than the sum (CTOT) of the individual transmission capacities (ci) of the channels (Ci), said transmission/reception being regulated by a system clock (CKS) and by an enable signal (En) able to generate a clock signal (CKSEn) with smaller fronts compared to the system clock (CKS), the method comprising the following steps: - defining a derived clock signal (CKSEn - CKS&En), comprising the fronts of the system clock (CKS) derived from enabling of the Enable signal (En); - defining a derived Enable signal (CKSEn/N) obtained from division by N of the fronts of the derived clock signal (CKSEn); - defining N status counters (Conti), each associated with a corresponding channel Ci, which count for ci up to cmax,; - defining N overflow registers (Ovfi) with binary values (0/1) each associated with a corresponding channel Ci; - defining a channel counter (CONTN) which assumes the sequence of values 0,1,2... , N-1; - defining N synchronization signals SYNCi each designed to enable sending of the units Uj to the corresponding channel Ci; - initializing the system at a time unit clock (CKU) by setting: all the status counters Conti = 0, all the overflow signals Ovfi = 0, the channel counter ContN = 0, all the signals SYNCi = 0 - incrementing at each front of the derived clock signal (CKSEn) enabled by the derived enable signal (CKSEn/N) the value of each channel counter ((Conti) by the value ci equal to the existing capacity of the channel Ci; - if Conti≥cmax forcing Conti=Conti-cmax, and - forcing the overflow signal of the channel Ci to 1, OVfi=1 - incrementing by one unit the value of the channel counter (ContN) at each front of the derived clock signal (CKSEn); - activating the signal SYNCi if the channel Ci corresponding to the existing value of the channel counter (ContN) is in overflow, i.e. Ovfi=1, - generating a signal (SyncTX;SyncRX) for enabling inputting of the data (Uj) from the source (TX;GRX) to the receiver (GTX;RX) able to determine sending of the existing signal Uj on/by the enabled channel Ci,